Semiconductor device
View Patent ↗The active region of an NMOS transistor and the active region of a PMOS transistor are divided by an STI element isolation structure. The STI element isolation structure is made up of a first element isolation structure formed so as to include the interval between both active regions, and a second element isolation structure formed in the region other than the first element isolation structure.
1. A semiconductor device comprising:
an element isolation structure in which trenches formed in an element isolation region on a semiconductor substrate are filled up with insulating materials;
a first conductivity type element formed in a first active region divided by said element isolation structure; and
a second conductivity type element formed in a second active region divided by said element isolation structure,
said element isolation structure comprising:
a first element isolation region of said element isolation region including regions adjacent to a pair of opposed ends of said second active region, said first element isolation region being filled with a first insulating material
a second element isolation region of said element isolation; other than said first element isolation region, said second element isolation region being filled with a second insulating material which is sparser than the first insulating material;
an upper layer portion of said first element isolation region is filled with said first insulating material; and
said first insulating material is an HDP silicon oxide and said second insulating material is nano clustering silica (NCS); and
wherein said first element isolation region is entirely surrounded by said first active region, said second active region and said second element isolation region.
2. The semiconductor device according to claim 1 , wherein a gate electrode is formed into a pattern on each of said first and second active regions with a gate insulating film being interposed, and the gate electrode on said second active region extends parallel to said first element isolation region.
3. The semiconductor device according to claim 1 , wherein either of said first and second conductivity type elements is a transistor, and said pair of opposed ends of said second active region are both ends of said second active region parallel to a width of a gate of the second conductivity type transistor.
4. The semiconductor device according to claim 1 , wherein first and second conductivity type elements are alternately arranged, and said first element isolation region is formed between each pair of first and second conductivity type elements.
5. The semiconductor device according to claim 1 , wherein a first conductivity type element group is constituted by a plurality of first conductivity type elements arranged, each second conductivity type element and said first conductivity type element group are formed in areas on said semiconductor substrate independent of each other, and said first element isolation region is formed so as to sandwich therein each second active region.
6. The semiconductor device according to claim 1 , wherein a first conductivity type element group constituted by a plurality of first conductivity type elements arranged and a second conductivity type element group constituted by a plurality of second conductivity type elements arranged are formed in areas on said semiconductor substrate independent of each other, and said first element isolation region is formed so as to sandwich therein each second active region of said second conductivity type element group.
7. The semiconductor device according to claim 1 , wherein only an upper layer portion of said first element isolation region is filled with said first insulating material.
8. The semiconductor device according to claim 1 , wherein upper and lower layer portions of said first element isolation region are filled with different insulating materials that give compressive stresses.
9. The semiconductor device according to claim 1 , wherein said first insulating material is one selected from a group of highly dense plasma oxide, oxide of amorphous silicon, and oxide of polycrystalline silicon, and said first insulating material is silicon oxide deposited at a temperature not more than its glass transition temperature.
10. The semiconductor device according to claim 1 , wherein said second element isolation region is filled with said second insulating material with a liner nitride film interposed.
11. The semiconductor device according to claim 5 , wherein dummy active regions are formed at both ends of each second conductivity type element.
12. The semiconductor device according to claim 6 , wherein dummy active regions are formed at both ends of said second conductivity type element group.
13. The semiconductor device according to claim 7 , wherein a lower layer portion of said first element isolation region is filled with the same insulating material as said second insulating material in said second element isolation region.