Organic light emitting display having improved via hole

1. A flat panel display, comprising:

a semiconductor layer formed on a substrate;

a first insulating layer formed on the substrate and including a contact hole;

an electrode formed on the first insulating layer and coupled to the semiconductor layer through the contact hole;

a second insulating layer formed on the first insulating layer and including a via hole; and

a pixel electrode formed on the second insulating layer and coupled to the electrode through the via hole,

wherein the via hole is formed corresponding to the contact hole and has a size larger than the contact hole, and

wherein the pixel electrode comprises:

a reflective layer arranged on the second insulating layer, and

a transparent conductive layer arranged on the reflective layer,

wherein the reflective layer comprises a first opening portion that exposes the electrode, and the transparent conductive layer is coupled to the electrode through the first opening portion.

2. The flat panel display of claim 1 , wherein the second insulating layer comprises a protective layer and an overcoat layer, the via hole being formed in the protective layer and the overcoat layer.

3. The flat panel display of claim 1 , wherein the second insulating layer comprises:

a protective layer formed on the first insulating layer and including a second opening portion that exposes the electrode; and

an overcoat layer formed on the protective layer and including a third opening portion that exposes the electrode,

wherein the via hole includes the second opening portion and the third opening portion, and the second opening portion and the third opening portion have a larger size than the contact hole.

4. The flat panel display of claim 3 , wherein a size of the second opening portion is greater than or equal to a size of the third opening portion.

5. The flat panel display of claim 1 , wherein the second insulating layer comprises an overcoat layer including an opening portion that exposes the electrode, and the via hole includes the opening portion, the opening portion having a larger size than the contact hole.

6. The flat panel display of claim 1 , wherein the electrode is a drain electrode of a thin film transistor.

7. The flat panel display of claim 1 , wherein:

a plan view area of the via hole overlaps a plan view area of the contact hole; and

at least a portion of a plan view area of the first opening portion is within the plan view area of the contact hole and the plan view area of the via hole.

8. The flat panel display of claim 7 , wherein the second insulating layer comprises a protective layer and an overcoat layer, and the via hole is formed in the protective layer and the overcoat layer.

9. The flat panel display of claim 7 , wherein the second insulating layer comprises:

a protective layer formed on the first insulating layer and including a second opening portion that exposes the electrode; and

an overcoat layer formed on the protective layer and including a third opening portion that exposes the electrode,

wherein the via hole includes the second opening portion and the third opening portion, and the second opening portion and the third opening portion have a larger size than the contact hole.

10. The flat panel display of claim 9 , wherein a size of the second opening portion is greater than or equal to a size of the third opening portion.

11. The flat panel display of claim 7 , wherein the pixel electrode further includes a transparent conductive layer formed on the reflective layer, and the transparent conductive layer electrically contacts the electrode through the first opening portion.

12. The flat panel display of claim 7 , wherein the electrode is a drain electrode of a thin film transistor.

13. A flat panel display, comprising:

a first conductive layer formed on a substrate;

a first insulating layer formed on the substrate and having a first opening portion;

a second conductive layer formed on the first insulating layer and coupled to the first conductive layer through the first opening portion;

a second insulating layer formed on the substrate and including a second opening portion; and

a third conductive layer formed on the second insulating layer and coupled to the second conductive layer through the second opening portion, the third conductive layer including a reflective layer having a third opening portion that exposes a part of the second conductive layer, the reflective layer arranged on the second insulating layer, and a transparent conductive layer arranged on the reflective layer and coupled to the second conductive layer through the third opening portion,

wherein at least a portion of a plan view area of the first opening portion is within a plan view area of the second opening portion, and the second opening portion has a larger size than the first opening portion.

14. The flat panel display of claim 13 , wherein the first insulating layer comprises an interlayer dielectric, and the second insulating layer comprises a protective layer and an overcoat layer.

15. The flat panel display of claim 13 , wherein the plan view area of the second opening portion overlaps the plan view area of the first opening portion, and at least a portion of a plan view area of the third opening portion is within the plan view area of the first opening portion and the plan view area of the second opening portion.

16. The flat panel display of claim 13 , wherein the first opening portion is a contact hole, and the second opening portion is a via hole.

17. The flat panel display of claim 13 , wherein the plan view area of the first opening portion is contained within the plan view area of the second opening portion.