IP Library Granted Patent US 7,384,826
Granted Patent B2
US 7,384,826 · App. 11/169,820 · Granted Jun 10, 2008

Method of forming ohmic contact to a semiconductor body

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Quick Facts
Patent No.
US 7,384,826
App. No.
11/169,820
Granted
Jun 10, 2008
Kind
B2
Abstract

A process for forming an ohmic contact on the back surface of a semiconductor body includes depositing a donor layer on the back surface of the semiconductor body followed by a sintering step to form a shallow intermetallic region capable of forming a low resistance contact with a contact metal.

Claims (45)

1. A method for fabricating a semiconductor device, comprising the steps of:

forming a field oxide atop an upper surface of a semiconductor body along a termination region;

etching a plurality of windows within said field oxide thereby forming spaced field oxide rings, said plurality of windows extending to said upper surface of said body;

forming components of the semiconductor device in said upper surface of said semiconductor body;

using said windows to form guard rings of P type conductivity within said upper surface of said body and further forming an oxide layer over each guard ring;

etching a window within each of said oxide layers to expose said underlying guard ring; forming separate stepped field plates over each of said field oxide rings, wherein each field plate contacts either an anode contact metal or a guard ring;

depositing on a back surface of said semiconductor body a metallic donor layer that includes atoms capable of forming an intermetallic composition having low contact resistivity;

heating said semiconductor body thereby forming an intermetallic region of low contact resistivity in said back surface of said body; and

depositing a contact metal over said intermetallic region thereby forming an ohmic contact.

2. The method of claim 1 , wherein said is a float zone silicon body.

3. The method of claim 2 , where said heating step heats said body at approximately 500° C. or less.

4. The method of claim 2 , wherein said intermetallic region has a depth of approximately 0.5 to 1.6 μm from said back surface of said body.

5. The method of claim 2 , wherein said donor layer includes an alloy selected from a group consisting of AuAs, AuSb, and AuSn.

6. The method of claim 2 , wherein said donor layer includes AuAs with 0.1 to 0.5% arsenic, AuSb with 10 to 30% antimony, or AuSn with 10 to 30% tin.

7. A method for fabricating a semiconductor device, comprising:

forming a field oxide atop an upper surface of a semiconductor body along a termination region;

etching a plurality of windows within said field oxide thereby forming spaced field oxide rings, said plurality of windows extending to said upper surface of said body;

forming a plurality of spaced P type conductivity regions within said upper surface of said semiconductor body along an active region thereof;

using said windows to form guard rings of P type conductivity within said upper surface of said body and further forming an oxide layer over each guard ring;

etching a window within each of said oxide layers to expose said underlying guard ring; and

forming separate stepped field plates over each of said field oxide rings:

depositing on a back surface of said semiconductor body a donor layer that includes one of AuAs alloy, AuSb alloy, an AuSn alloy;

heating said semiconductor body thereby forming an intermetallic region of low contact resistivity in said back surface of said body;

depositing a contact metal over said intermetallic region thereby forming an ohmic contact; and

depositing an anode contact metal atop said upper surface along said active region such that said anode contact metal contacts said spaced P regions and said upper surface, thereby forming a plurality of PN diodes and Schottky contacts therebetween, wherein each field plate contacts either said anode contact metal or a guard ring.

8. The method of claim 7 , further comprising the steps of:

forming a ring of N type conductivity within said upper surface of said body at an outer periphery of said termination region; and

forming an amorphous silicon layer over each of said field plates.

9. The method of claim 7 , wherein said semiconductor device has a thickness of 75 μm or less.

10. A method for fabricating a semiconductor device, comprising:

forming a field oxide atop an upper surface of a semiconductor body along a termination region;

etching a plurality of windows within said field oxide thereby forming spaced field oxide rings, said plurality of windows extending to said upper surface of said body;

forming components of the semiconductor device in said upper surface of said semiconductor body;

using said windows to form guard rings of P type conductivity within said upper surface of said body and further forming an oxide layer over each guard ring;

etching a window within each of said oxide layers to expose said underlying guard ring; and

forming separate stepped field plates over each of said field oxide rings, wherein each field plate contacts either an anode contact metal or a guard ring;

depositing a first layer of titanium or titanium-tungsten on a back surface of said body;

depositing on said first layer a donor layer that includes atoms capable of forming an intermetallic composition having low contact resistivity;

heating said semiconductor body thereby forming an intermetallic region of low contact resistivity in said back surface of said body; and

depositing a contact metal over said intermetallic region thereby forming an ohmic contact.

11. The method of claim 1 , wherein said semiconductor body is either a silicon carbide body or a gallium nitride body.

12. The method of claim 11 , where said heating step heats said body at 350° C. to 450° C.

13. The method of claim 11 , wherein said donor layer includes atoms of SbAu.

14. The method of claim 11 , wherein said donor layer includes atoms of SbAu with 30% antimony.

15. The method of claim 13 , wherein said donor layer is deposited to a thickness of 3000 Å or less.

Assignments (2)
CHANGE OF NAME Recorded Jul 23, 2018
From: INTERNATIONAL RECTIFIER CORPORATION
To: INFINEON TECHNOLOGIES AMERICAS CORP.
Reel/Frame 046612/0968 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 29, 2005
From: RICHIERI, GIOVANNI
To: INTERNATIONAL RECTIFIER CORPORATION
Reel/Frame 016742/0831 →