IP Library Granted Patent US 7,206,707
Granted Patent B1
US 7,206,707 · App. 11/170,121 · Granted Apr 17, 2007

Wideband digital IFM receiver

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Quick Facts
Patent No.
US 7,206,707
App. No.
11/170,121
Granted
Apr 17, 2007
Kind
B1
Abstract

An IFM receiver includes a hybrid for outputting I and Q signals from a received input signal; a first ADC for digitizing the I signal to produce a first digital signal at a sampling rate of 1/τ, and a second ADC for digitizing the Q signal to produce a second digital signal at the same sampling rate. A processor is configured to (a) delay the first and second digital signals by at least one sample time of τ, (b) count the number of samples produced having predetermined phase shifts, and (c) determine the frequency of the received input signal, based on the number of samples having the predetermined phase shifts. The first and second ADCs are each 1-bit analog-to-digital converters. The predetermined phase shifts of 0°, 90°, −90° and 180° are counted by the processor over a predetermined time interval.

Claims (71)

1. An instantaneous frequency measurement (IFM) receiver comprising

a hybrid for outputting I and Q signals from a received input signal,

a first analog-to-digital converter (ADC) for digitizing the I signal to produce a first digital signal at a sampling rate of 1/τ, where τ is a sample time,

a second ADC for digitizing the Q signal to produce a second digital signal at the same sampling rate of 1/τ,

the first and second ADCs are each 1-bit analog-to-digital converters,

a processor configured to delay the first and second digital signals by one sample time of τ, and count numbers of samples produced having predetermined phase shifts, and

the processor configured to determine a frequency of the received input signal, based on the number of samples having the predetermined phase shifts, and provide the determined frequency to a user.

2. The IFM receiver of claim 1 including

a sampling clock coupled to each ADC for sampling each ADC at a rate of 1/τ.

3. The IFM receiver of claim 1 wherein

the processor is configured to count the number of samples having the predetermined phase shifts of 0°, 90°, −90° and 180° over a predetermined time interval.

4. The IFM receiver of claim 3 wherein

one τ is a delay time between two adjacent sampling intervals, and

180° is a maximum phase shift between two adjacent sampling times.

5. The IFM receiver of claim 1 wherein

the first and second digital signals are combined to form real and imaginary components of (x, y) where

(1, 1) represents an angle between 0° and 90°,

(−1, 1) represents an angle between 90° and 180°,

(−1, 1) represents an angle between 180° and 270°, and

(−1, −1) represents an angle between 270° and 360°.

6. The IFM receiver of claim 1 wherein

the processor is configured to delay the first and second digital signals by at least one of 2τ, 4τ, 8τ, 16τ, 32τ, or 64τ, in addition to the 1τ sample time, and

the processor is configured to count the number of samples produced having predetermined phase shifts at the at least one of 2τ, 4τ, 8τ, 16τ, 32τ, or 64τ, in addition to the 1τ sample time.

7. The IFM receiver of claim 6 including

a look up table (LUT) for access by the processor, wherein

the LUT includes values of numbers of samples at predetermined phase shifts of 0°, 90°, −90° and 180° as a function of input frequency for determining the frequency of the received input signal.

8. The IFM receiver of claim 7 wherein

the LUT includes values of number of samples of n23 and n14 as a function of frequency having the following relationship:

n 23 =n 2 −n 3

n 14 =n 1 −n 4

where

n1 is the number of samples counted with a predetermined phase shift of 0°,

n2 is the number of samples counted with a predetermined phase shift of 90°,

n3 is the number of samples counted with a predetermined phase shift of −90°, and

n4 is the number of samples counted with a predetermined phase shift of 180°.

9. A method of determining a frequency of a signal in an IFM receiver, comprising the steps of:

(a) receiving, by a hybrid, a signal S to form I and Q signals;

(b) sampling the I and Q signals, by respective one-bit ADCs, to form digital I and Q signals, and combining the digital I and Q signals to form a combined signal C;

(c) delaying, by a processor, C from itself by one sample time τ;

(d) counting, by the processor, numbers of samples having predetermined phase shifts, after delaying C;

(e) determining, by the processor, the frequency of the signal S, based on the number of samples counted in step (d); and

(f) providing the determined frequency to a user.

10. The method of claim 9 wherein

step (b) includes sampling the I and Q signals at a sampling rate of 1/τ.

11. The method of claim 9 wherein

step (d) includes counting the number of samples having the predetermined phase shifts of 0°, 90°, −90° and 180° over a predetermined interval of time.

12. The method of claim 9 including the steps of:

storing a look up table (LUT) with values of numbers of samples at the predetermined phase shifts of 0°, 90°, −90° and 180° as a function of frequency; and

determining the frequency of the received input signal, based on the values stored in the LUT.

13. The method of claim 12 including the step of:

incorporating, into the LUT, values of numbers of samples of n23 and n14 as a function of frequency having the following relationship:

n 23 =n 2− n 3

n 14 =n 1 −n 4

where

n1 is the number of samples counted with a predetermined phase shift of 0°,

n2 is the number of samples counted with a predetermined phase shift of 90°,

n3 is the number of samples counted with a predetermined phase shift of −90°, and

n4 is the number of samples counted with a predetermined phase shift of 180°.

14. The method of claim 9 wherein

step (c) includes delaying the signal C from itself by at least one of 2τ, 4τ, 8τ, 16τ, 32τ, or 64τ, in addition to the 1τ sample time, and

step (d) includes counting the number of samples produced having predetermined phase shifts at the at least one of 2τ, 4τ, 8τ, 16τ, 32τ, or 64τ, in addition to the 1τ sample time.

15. A method of determining a frequency of a signal comprising the steps of:

(a) receiving a signal S;

(b) forming in-phase (I) and quadrature (Q) signals from the signal S;

(c) sampling the I and Q signals, using one bit ADCs during a predetermined time interval, to form first and second digital signals;

(d) combining the first and second digital signals to form a combined signal C;

(e) delaying C from itself by one sample time τ;

(f) counting numbers of samples having predetermined phase shifts of 0°, 90°, −90° and 180°, after delaying C; and

(g) determining the frequency of the signal S, based on the number of samples counted in step (f) at each of the predetermined phase shifts, and providing the determined frequency to a user.

16. The method of claim 15 wherein

step (g) includes comparing the number of samples counted in step (f) at each of the predetermined phase shifts with respective numbers of samples stored in a LUT to determine the frequency of the signal S.

Assignments (2)
MERGER Recorded Jul 1, 2016
From: EXELIS INC.
To: HARRIS CORPORATION
Reel/Frame 039362/0534 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 27, 2012
From: ITT MANUFACTURING ENTERPRISES, LLC (FORMERLY KNOWN AS ITT MANUFACTURING ENTERPRISES, INC.)
To: EXELIS, INC.
Reel/Frame 027604/0001 →