Shift register without noise and liquid crystal display device having the same

1. A shift register structure comprising:

a shift register configured to receive a start signal and at least a clock signal as input signals, and configured to output the clock signal as an output signal on an output terminal and sequentially output a cascaded clock signal as the start signal for next stages, wherein the clock signal and the cascaded clock signal are provided by different transistors, which are separate each other; and

cleaner means for receiving the start signal for removing noise included in the start signal.

2. The shift register structure of claim 1 , wherein the shift register is formed of an amorphous semiconductor device.

3. The shift register structure of claim 1 , wherein the cleaner means is a cleaner transistor for receiving the start signal.

4. The shift register structure of claim 1 , wherein the shift register receives the clock signal of two phases.

5. The shift register structure of claim 1 , wherein the shift register receives the clock signal of three phases.

6. The shift register structure of claim 1 , wherein the start signal is a start voltage provided at a first stage and at the cascaded clock signal of a previous stage.

7. The shift register structure of claim 1 , wherein the cleaner means is a cleaner transistor including a gate configured to receive the clock signal.

8. The shift register structure of claim 1 , wherein the cleaner means is a cleaner transistor including a gate coupled to the shift register.

9. The shift register structure of claim 1 , wherein the different transistors include a T7 transistor outputting the clock signal on an output terminal, and a T9 transistor outputting the cascaded clock signal as the start signal of a next stage.

10. The shift register structure of claim 9 , the shift register further comprising a T8 transistor coupled to a gate of the cleaner means, which is a cleaner transistor.

11. The shift register structure of claim 10 , wherein the shift register further comprises:

a T1 transistor including a gate to which the start voltage is applied, a source to which a driving voltage is applied, and a drain connected to a first node;

a T2 transistor including a gate and a source to which the driving voltage is applied, and a drain connected to a second node;

a T4 transistor including a gate connected to an output terminal of a shift register of a next stage and a source connected to the first node, for discharging the first node and charging the second node; and

a T5 transistor including a gate connected to the first node and a source connected to the second node, for discharging the second node;

wherein the T7 transistor includes a gate connected to the first node, a source connected to the clock signal, and a drain connected to the output terminal, for outputting the clock signal to the output terminal;

wherein the T8 transistor includes a gate connected to the second node and a source connected to the output terminal, for lowering the clock signal outputted by the T7 transistor to a low potential.

12. A liquid crystal display (LCD) device comprising:

a liquid crystal panel having pixels defined by gate lines and data lines and thin film transistors formed in each pixel, for displaying an image;

a shift register comprising:

a T7 transistor configured to output a clock signal on an output terminal;

a T9 transistor configured to output a cascaded clock signal as a start voltage of a next stage, wherein the clock signal and the cascaded clock signal are isolated from each other; and

cleaner means for removing noise from the cascaded clock signal.

13. The LCD device of claim 12 , wherein the shift register further comprises:

a T1 transistor including a gate to which a start voltage is applied, a source to which a driving voltage is applied, and a drain connected to a first node;

a T2 transistor including a gate and a source to which the driving voltage is applied, and a drain connected to a second node;

a T4 transistor including a gate connected to an output terminal of a shift register of a next stage and a source connected to the first node, for discharging the first node and charging the second node;

a T5 transistor including a gate connected to the first node and a source connected to the second node, for discharging the second node;

the T7 transistor including a gate connected to the first node, a source connected to the clock signal, and a drain connected to the output terminal, for outputting the clock signal to the output terminal; and

a T8 transistor including a gate connected to the second node and a source connected to the output terminal, for lowering the clock signal passed by the T7 transistor to a low potential.

14. The LCD device of claim 12 , wherein the cleaner means comprises a cleaner transistor that is provided with the cascaded clock signal.

15. The LCD device of claim 12 , wherein the cleaner means comprises a cleaner transistor that is provided with a voltage charged to the second node.

16. The LCD device of claim 12 , further comprising:

a clock generating unit for applying the clock signal to the shift register; and

a data driving unit for applying image information to the liquid crystal panel.

17. The LCD device of claim 16 , wherein the cleaner means is a cleaner transistor comprising a gate, a source and a drain,

the gate of the cleaner transistor is connected to the clock generating unit, the drain of the cleaner transistor is grounded.

18. The LCD device of claim 12 , wherein the shift register is formed at the liquid crystal panel.

19. The LCD device of claim 12 , wherein the shift register is formed of an amorphous semiconductor device.

20. A method of a driving a shift register for an LCD comprising:

providing a starter voltage as an input to the shift register;

outputting a clock signal on an output terminal;

sequentially outputting the cascaded clock signal as a starter voltage of a next shift register; and

inputting the starter voltage to a circuit element for removing noise from the starter voltage, wherein the clock signal on the output terminal is provided by an element separate from an element providing the cascaded clock signal.

21. The method of claim 20 , wherein the circuit element comprises a cleaner transistor operative to remove noise from the starter voltage.

22. A shift register structure comprising:

a shift register for sequentially outputting voltages in stages, wherein the shift register comprises:

a T9 transistor for outputting a clock signal of the shift register as a start voltage of a next stage by being synchronized with an output signal on an output terminal of the shift register;

a T1 transistor including a gate to which a start voltage of the shift register is applied, a source to which a driving voltage is applied, and a drain connected to a first node;

a T2 transistor including a gate and a source to which the driving voltage is applied, and a drain connected to a second node;

a T4 transistor including a gate connected to an output terminal of a shift register of a next stage and a source connected to the first node, for discharging the first node and charging the second node;

a T5 transistor including a gate connected to the first node and a source connected to the second node, for discharging the second node;

a T7 sixth transistor including a gate connected to the first node, a source receiving the clock signal, and a drain connected to an output terminal, for passing the clock signal to the output terminal;

a T8 transistor including a gate connected to the second node and a source connected to the output terminal, for lowering the clock signal outputted by the T7 sixth transistor to a low potential; and

a cleaner transistor turned on by the clock signal and operative to remove noise from the start voltage of the sift register or the shift register of the next stage.