IP Library Granted Patent US 7,219,022
Granted Patent B2
US 7,219,022 · App. 11/171,789 · Granted May 15, 2007

Methods and apparatus for detecting failure of an isolation device

Assignee: Allegro Microsystems, Inc.
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Quick Facts
Patent No.
US 7,219,022
App. No.
11/171,789
Granted
May 15, 2007
Kind
B2
Abstract

Apparatus for detecting failure of an isolation device includes a current sensor to sense current through the isolation device and a circuit responsive to the current sensor output signal and to an enable signal that controls the isolation device for providing an Early Failure Warning (EFW) signal indicative of whether the isolation device has failed. The enable signal is at a first logic level when the isolation device is on and is brought to a second logic level to disable and test the isolation device. Also described is a method of detecting a failure of an isolation device including disabling the isolation device, sensing a current through the isolation device, and providing an EFW signal indicating that the isolation device has failed if the current through the isolation device is greater than a predetermined level when the isolation device is disabled.

Claims (28)

1. Apparatus for detecting failure of an isolation device, comprising:

a switch coupled between a bus and a load and responsive to an enable signal;

a current sensor coupled in series with the switch to provide a current sensor output signal indicative of the level of current through the switch;

a comparator having a first input responsive to the current sensor output signal, a second input coupled to a reference voltage, and an output at which is provided a control signal indicative of whether the current through the switch is greater than a predetermined level established by the reference voltage; and

a logic circuit responsive to the control signal and to the enable signal for providing an EFW signal indicative of whether the switch has failed.

2. The apparatus of claim 1 further comprising a delay element for delaying the enable signal to provide a delayed enable signal to the logic circuit.

3. The apparatus of claim 2 wherein the logic circuit comprises an AND gate responsive to the delayed enable signal and to the current sensor output signal.

4. The apparatus of claim 1 further comprising a second comparator having a first input responsive to a sensor output signal, a second input coupled to a second reference voltage, and an output at which is provided a second control signal indicative of whether the sensor output signal is greater than a second predetermined level established by the second reference voltage.

5. The apparatus of claim 4 wherein the sensor output signal is provided by the current sensor output signal and further comprising a second logic circuit responsive to the second control signal and to the enable signal for generating a drive signal to cause the switch to turn on when the current through the switch is less than the second predetermined level and the enable signal is at a predetermined logic level.

6. The apparatus of claim 5 wherein the second logic circuit comprises an AND gate responsive to the second control signal and to the enable signal.

7. The apparatus of claim 4 wherein the sensor output signal is provided by a voltage at the load.

8. The apparatus of claim 4 wherein the sensor output signal is provided by a temperature sensor.

9. A method of detecting a failure of an isolation device coupled between a bus and a load, comprising:

disabling the isolation device;

sensing a current through the isolation device; and

providing an EFW signal indicating that the isolation device has failed if the current through the isolation device is greater than a predetermined level when the isolation device is disabled.

10. The method of claim 9 wherein disabling the isolation device includes providing an enable signal to the isolation device, the enable signal being at a first logic level to enable the isolation device and being at a second logic level to disable the isolation device.

11. The method of claim 10 further comprising delaying the enable signal to provide a delayed enable signal.

12. The method of claim 11 further comprising providing a comparator output signal indicative of whether the current through the isolation device is greater than a predetermined level.

13. The method of claim 12 wherein providing the EFW signal includes providing an AND gate responsive to the delayed enable signal and to the comparator output signal.

14. Apparatus for detecting failure of an isolation device coupled between a bus and a load comprising:

a current sensor coupled to provide a current sensor output signal indicative of a current through the isolation device; and

a circuit responsive to the current sensor output signal and to an enable signal that controls the isolation device for providing an EFW signal indicative of whether the isolation device has failed.

15. The apparatus of claim 14 wherein the circuit comprises

a comparator having a first input responsive to the current sensor output signal, a second input coupled to a reference voltage, and an output at which is provided a control signal indicative of whether the output current Iout is greater than a predetermined level established by the reference voltage; and

a logic circuit responsive to the comparator output signal and to the enable signal for providing an EFW signal indicative of whether the isolation device has failed.

16. The apparatus of claim 15 further comprising a delay element for delaying the enable signal to provide a delayed enable signal to the logic circuit.

17. The apparatus of claim 16 wherein the logic circuit comprises an AND gate responsive to the delayed enable signal and to the current sensor output signal.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS AT REEL 053957/FRAME 0874 Recorded Nov 1, 2023
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
To: ALLEGRO MICROSYSTEMS, LLC
Reel/Frame 065420/0572 →
RELEASE OF SECURITY INTEREST IN PATENTS (R/F 053957/0620) Recorded Jun 22, 2023
From: MIZUHO BANK, LTD., AS COLLATERAL AGENT
To: ALLEGRO MICROSYSTEMS, LLC
Reel/Frame 064068/0360 →
PATENT SECURITY AGREEMENT Recorded Jun 22, 2023
From: ALLEGRO MICROSYSTEMS, LLC
To: MORGAN STANLEY SENIOR FUNDING, INC., AS THE COLLATERAL AGENT
Reel/Frame 064068/0459 →
PATENT SECURITY AGREEMENT Recorded Oct 1, 2020
From: ALLEGRO MICROSYSTEMS, LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 053957/0874 →
PATENT SECURITY AGREEMENT Recorded Oct 1, 2020
From: ALLEGRO MICROSYSTEMS, LLC
To: MIZUHO BANK LTD., AS COLLATERAL AGENT
Reel/Frame 053957/0620 →
CONVERSION AND NAME CHANGE Recorded Apr 10, 2013
From: ALLEGRO MICROSYSTEMS, INC.
To: ALLEGRO MICROSYSTEMS, LLC
Reel/Frame 030426/0178 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2005
From: WEKHANDE, SHASHANK S.
To: ALLEGRO MICROSYSTEMS, INC.
Reel/Frame 016748/0211 →
Continuity (1)
Related Publication 20070005274A1 · Jan 4, 2007