Superjunction semiconductor device
View Patent ↗A superjunction semiconductor device includes an edge p pillar, an active region, and a termination region. The edge p pillar has a rectangular ring shape with rounded corners surrounding the active region. The active region includes an active n region and active p pillars having vertical stripe shapes disposed at regular intervals in the active n region. The top and bottom ends of the active p pillars are separated from the edge p pillar. The termination region includes termination n pillars and termination p pillars alternately arranged around the edge p pillar. Surplus p charges that are not used to balance the quantity of p charges and the quantity of n charges among p charges included in the upper and lower parts of the edge p pillar are eliminated or n charges are supplemented to balance the quantity of p charges and the quantity of n charges.
1. A superjunction semiconductor device comprising:
an edge p pillar having a rectangular ring shape with rounded corners;
an active region surrounded by the edge p pillar, the active region having active p pillars arranged in an n region so as to form alternating active p and n pillars in the active region, the active p pillars having a stripe shape and extending in parallel along a vertical dimension with top and bottom ends separated from the edge p pillar;
a termination region surrounding the edge p pillar; and
one or more subsidiary p pillars each having a top end and a bottom end, the one or more subsidiary p pillars being disposed in the n region between a first active p pillar and a second active p pillar, a top end of the first active p pillar being lower, along the vertical dimension, than a top end of the second active p pillar, the one or more subsidiary p pillars being located between the top end of the first active p pillar and the top end of the second active p pillar such that the bottom end of each of the one or more subsidiary p pillars does not extend below the top end of the first p pillar, and the top end of each of the one or more subsidiary p pillars does not extend above the top end of the second p pillar, wherein a width of the bottom end of each of the one or more subsidiary p pillars is narrower than a width of the n pillars at the bottom end of the one or more subsidiary p pillars along a dimension perpendicular to the vertical dimension.
2. The superjunction semiconductor device of claim 1 , wherein a distance between the central axis of a horizontally extending portion of the edge p pillar and the top end of a plurality of the active p pillars is equal to half the distance between the vertical central axes of neighboring active p pillars.
3. The superjunction semiconductor device of claim 2 , wherein a distance between the central axis of a vertically extending portion of the edge p pillar and the vertical central axis of the corresponding active p pillar disposed closest to the vertically extending portion of the edge p pillar is identical to the distance between the vertical central axes of neighboring active p pillars.
4. The superjunction semiconductor device of claim 1 , wherein a width of the edge p pillar is identical to a width of each of the active p pillars.
5. A superjunction semiconductor device comprising:
an active region surrounded by an edge p pillar, the active region including active p pillars in the shape of stripes that extend in parallel along a vertical dimension, the active p pillars being arranged in an n region so as to form alternating active p and n pillars in the active region, the active p pillars being spaced from the edge p pillar,
wherein a width of an upper portion of a first one of the active p pillars in a corner of the active region gradually increases along the vertical dimension toward an end of the first one of the active p pillars so that a width of the first one of the active p pillars at the end of the first one of the active p pillars is wider than a width of a middle section of the first one of the active p pillars, wherein the width of an upper portion of a first one of the active p pillars and the width of a middle section of the first one of the active p pillars extend along a dimension perpendicular to the vertical dimension.
6. The superjunction semiconductor device of claim 5 , wherein a width of upper and lower portions of the active p pillars are gradually increased in the corners of the active region to compensate for lower quantity of p charges than quantity of n charges in the corners of the active region.
7. The superjunction semiconductor device of claim 5 further comprising a termination region including termination n pillars and termination p pillars alternately arranged around the edge p pillar.
8. The superjunction semiconductor device of claim 1 , wherein the subsidiary p pillars are bar shaped and are vertically arranged in the corners of the active region.
9. The superjunction semiconductor device of claim 1 , wherein the subsidiary p pillars are in the form of islands arranged at predetermined intervals in the corners of the active region.
10. The superjunction semiconductor device of claim 1 , wherein the subsidiary p pillars are in the shape of a bent belt and extend parallel to the edge p pillar.
11. The superjunction semiconductor device of claim 1 , wherein the termination region includes alternately arranged termination n pillars and termination p pillars.
12. The superjunction semiconductor device of claim 5 , wherein a distance between a central axis of a horizontally extending portion of the edge p pillar and a top end of a plurality of the active p pillars is equal to half the distance between the vertical central axes of neighboring active p pillars.
13. The superjunction semiconductor device of claim 12 , wherein a distance between a central axis of a vertically extending portion of the edge p pillar and the vertical central axis of a corresponding active p pillar disposed closest to the vertically extending portion of the edge p pillar is identical to the distance between the vertical central axes of neighboring active p pillars.
14. The superjunction semiconductor device of claim 5 , wherein a width of the edge p pillar is identical to a width of each of the active p pillars.
15. The superjunction semiconductor device of claim 5 , wherein a width of an upper portion of a second one of the active p pillars in the corner of the active region gradually decreases toward an end of the second one of the active p pillars.