Integrated circuit tolerant to the locking phenomenon
Integrated circuit comprising doped zones ( 3 to 8 ) formed in a substrate ( 1, 2 ), forming a parasitic thyristor structure with two parasitic bipolar transistors (T 1 , T 2 ), the integrated circuit comprising two metallizations ( 16, 19 ) interconnecting each of the two corresponding doped zones ( 4, 5; 6, 7 ) of the integrated circuit, to reduce the base resistances (R P− , R P− ) of the two bipolar transistors, at least one of the metallizations ( 16, 19 ) performed to reduce the base resistances (R N− , R P− ) of the two bipolar transistors, being connected to a power supply metallization ( 15, 16 ) in the integrated circuit, entirely through the substrate ( 1, 2 ).
1. An integrated circuit comprising:
a substrate;
a plurality of doped zones formed in the substrate so as to form a plurality of parasitic thyristor structures that each include two parasitic bipolar transistors;
a plurality of first metallizations and a plurality of second metallizations, each of the first metallizations interconnecting two of the doped zones of one of the parasitic thyristor structures and a each of the second metallizations interconnecting another two of the doped zones of one of the parasitic thyristor structures, so as to reduce base resistances of the two bipolar transistors;
a first power supply metallization; and
a second power supply metallization,
wherein none of the first metallizations is directly connected to the first or second power supply metallization,
at least two of the first metallizations are directly connected by a third metallization,
none of the second metallizations is directly connected to the first or second power supply metallization, and
at least two of the second metallizations are directly connected by a fourth metallization.
2. The integrated circuit according to claim 1 ,
wherein all of the first metallizations are connected to the first power supply metallization entirely through the substrate, and
all of the second metallizations are connected to the second power supply metallization entirely through a well that is formed in the substrate.
3. The integrated circuit according to claim 2 , wherein the two doped zones interconnected by each of the first metallizations are placed as close as possible to each other.
4. The integrated circuit according to claim 3 , further comprising:
a plurality of first and second MOS transistors with different channel types, the first MOS transistor being formed in the substrate and the second MOS transistor being formed in the well that is formed in the substrate,
wherein each of the first and second MOS transistors with different channel types form the bipolar transistors of one of the parasitic thyristor structures.
5. The integrated circuit according to claim 1 , wherein the two doped zones interconnected by each of the first metallizations are placed as close as possible to each other.
6. The integrated circuit according to claim 1 , further comprising:
a plurality of first and second MOS transistors with different channel types, the first MOS transistor being formed in the substrate and the second MOS transistor being formed in a well that is formed in the substrate,
wherein each of the first and second MOS transistors with different channel types form the bipolar transistors of one of the parasitic thyristor structures.
7. An integrated circuit comprising:
a substrate;
a plurality of doped zones formed in the substrate so as to form a plurality of parasitic thyristor structures, each of the parasitic thyristor structures including two parasitic bipolar transistors;
a plurality of first metallizations and a plurality of second metallizations, each of the first metallizations interconnecting two of the doped zones of one of the parasitic thyristor structures and each of the second metallizations interconnecting another two of the doped zones of one of the parasitic thyristor structures, so as to reduce base resistances of the two bipolar transistors of the parasitic thyristor structures;
a first power supply metallization; and
a second power supply metallization,
wherein all of the first metallizations are connected to the first power supply metallization entirely through the substrate,
at least two of the first metallizations are directly connected by a third metallization so as to reduce a resistance between the first metallizations and the first power supply metallization,
all of the second metallizations are connected to the second power supply metallization entirely through one of the substrate and a well that is formed in the substrate, and
at least two of the second metallizations are directly connected by a fourth metallization so as to reduce a resistance between the second metallizations and the second power supply metallization.
8. The integrated circuit according to claim 7 , wherein all of the second metallizations are directly connected by the fourth metallization.
9. The integrated circuit according to claim 8 , wherein all of the first metallizations are directly connected by the third metallization.
10. The integrated circuit according to claim 8 , wherein the two doped zones interconnected by each of the first metallizations are placed as close as possible to each other.
11. The integrated circuit according to claim 7 ,
wherein each of the first metallizations directly connects a first of the doped zones that is a source of a MOS transistor to a second of the doped zones that is adjacent to the first doped zone and oppositely-doped, and
each of the second metallizations directly connects a third of the doped zones that is a source of another MOS transistor to a fourth of the doped zones that is adjacent to the third doped zone and oppositely-doped.
12. The integrated circuit according to claim 7 , further comprising:
a plurality of pairs of MOS transistors with different channel types, a first MOS transistor of each pair being formed in the substrate and a second MOS transistor of each pair being formed in the well that is formed in the substrate,
wherein each of the pairs of MOS transistors form the bipolar transistors of one of the parasitic thyristor structures, and
all of the second metallizations are connected to the second power supply metallization entirely through the well that is formed in the substrate.
13. The integrated circuit according to claim 7 , further comprising:
a well that is formed in the substrate,
wherein some of the doped zones are formed in the well that is formed in the substrate and others of the doped zones are formed in the substrate outside of the well, and
all of the second metallizations are connected to the second power supply metallization entirely through the well that is formed in the substrate.
14. The integrated circuit according to claim 13 ,
wherein all of the second metallizations are directly connected by the fourth metallization, and
all of the first metallizations are directly connected by the third metallization.
15. An information processing system including a plurality of integrated circuits, at least one of the integrated circuits comprising:
a substrate;
a plurality of doped zones formed in the substrate so as to form a plurality of parasitic thyristor structures that each include two parasitic bipolar transistors;
a plurality of first metallizations and a plurality of second metallizations, each of the first metallizations interconnecting two of the doped zones of one of the parasitic thyristor structures and each of the second metallizations interconnecting another two of the doped zones of one of the parasitic thyristor structures, so as to reduce base resistances of the two bipolar transistors;
a first power supply metallization; and
a second power supply metallization,
wherein none of the first metallizations is directly connected to the first or second power supply metallization,
at least two of the first metallizations are directly connected by a third metallization,
none of the second metallizations is directly connected to the first or second power supply metallization, and
at least two of the second metallizations are directly connected by a fourth metallization.
16. The information processing system according to claim 15 ,
wherein all of the first metallizations of the one integrated circuit are connected to the first power supply metallization entirely through the substrate, and
all of the second metallizations of the one integrated circuit are connected to the second power supply metallization entirely through a well that is formed in the substrate.
17. The information processing system according to claim 16 , wherein the two doped zones interconnected by each of the first metallizations of the one integrated circuit are placed as close as possible to each other.
18. The information processing system according to claim 17 , wherein the one integrated circuit further comprises:
a plurality of first and second MOS transistors with different channel types, the first MOS transistor being formed in the substrate and the second MOS transistor being formed in the well that is formed in the substrate,
wherein each of the first and second MOS transistors with different channel types form the bipolar transistors of one of the parasitic thyristor structures.
19. The information processing system according to claim 15 , wherein the two doped zones interconnected by each of the first metallizations of the one integrated circuit are placed as close as possible to each other.
20. The information processing system according to claim 15 , wherein the one integrated circuit further comprises:
a plurality of first and second MOS transistors with different channel types, the first MOS transistor being formed in the substrate and the second MOS transistor being formed in a well that is formed in the substrate,
wherein each of the first and second MOS transistors with different channel types form the bipolar transistors of one of the parasitic thyristor structures.