ESD configuration for low parasitic capacitance I/O
View Patent ↗An I/O ESD protection configuration of an integrated circuit that includes an ESD protection circuit connected between an I/O pad and an internal circuit at a first node and to an inductor at a second node. The inductor is connected between the second node and an external power supply. The external power supply provides a high reverse bias voltage across a diode of the ESD protection circuit. An ESD clamp is connected between the second node and a ground. An ESD discharge current is shunted through the ESD protection circuit and through the ESD clamp during a positive I/O ESD event. The inductor can be chosen to tune out a parasitic capacitance of the ESD clamp. The inductor can also block high frequency signals between the I/O pad and the external power supply, thereby minimizing the parasitic capacitance of the diode of the ESD protection circuit at high frequency.
1. An integrated circuit comprising,
an internal circuit connected between a first voltage supply and a second voltage supply and to an input-output (I/O) pad;
an electrostatic discharge (ESD) protection circuit connected between the I/O pad and the internal circuit at a first node and to an inductor at a second node, wherein the inductor is connected between the second node and a third voltage supply; and
an ESD clamp connected between the second node and the second supply voltage.
2. The integrated circuit of claim 1 , wherein an ESD discharge current is shunted through the ESD protection circuit and through the ESD clamp during a positive I/O ESD event.
3. The integrated circuit of claim 1 , wherein the internal circuit provides a discharge path during a negative I/O ESD event.
4. The integrated circuit of claim 1 , further comprising an additional ESD protection circuit connected between the first node and the second supply voltage.
5. The integrated circuit of claim 1 , wherein:
the first voltage supply provides a positive voltage;
the second voltage supply is a ground; and
the third voltage supply provides a positive voltage greater than the positive voltage provided by the first voltage supply.
6. The integrated circuit of claim 1 , wherein the third supply voltage provides a relatively high reverse bias voltage across a diode of the ESD protection circuit, thereby reducing a parasitic capacitance of the diode.
7. The integrated circuit of claim 1 , wherein the inductor has an inductance chosen to tune out a parasitic capacitance of the ESD clamp.
8. The integrated circuit of claim 1 , wherein the inductor has an inductance chosen to act as a high impedance element between the third supply voltage and the I/O pad at relatively high frequency.
9. The integrated circuit of claim 1 , wherein the inductor comprises a discrete component external to the integrated circuit.
10. The integrated circuit of claim 1 , wherein the inductor comprises a package component internal to the integrated circuit.
11. The integrated circuit of claim 1 , wherein the inductor comprises a package inductance that is characteristic of the integrated circuit.
12. The integrated circuit of claim 1 , wherein the inductor comprises a discrete component internal to the integrated circuit.
13. The integrated circuit of claim 1 , further comprising an additional ESD clamp connected in parallel to the internal circuit, between the first voltage supply and the second voltage supply.
14. An integrated circuit comprising,
an internal circuit connected between a first voltage supply and a second voltage supply and to an I/O pad;
a first ESD protection circuit connected between the I/O pad and the internal circuit at a first node and to a first inductor at a second node;
a second ESD protection circuit connected to the first node and to a second inductor at a third node; and
a first ESD clamp, connected between the second node and the second voltage supply, and a second ESD clamp, connected between the third node and the second voltage supply,
wherein the first inductor is connected between the second node and a third voltage supply and the second inductor is connected between the third node and a fourth voltage supply.
15. The integrated circuit of claim 14 , wherein:
the first voltage supply provides a positive voltage;
the second voltage supply is a ground;
the third voltage supply provides a positive voltage greater than the positive voltage provided by the first voltage supply; and
the fourth voltage supply provides a negative voltage.
16. The integrated circuit of claim 14 , wherein:
the first inductor has an inductance chosen to tune out a parasitic capacitance of the first ESD clamp; and
the second inductor has an inductance chosen to tune out a parasitic capacitance of the second ESD clamp.
17. The integrated circuit of claim 14 wherein:
the first inductor has an inductance chosen to act as a high impedance element between the third supply voltage and the I/O pad at relatively high frequency; and
the second inductor has an inductance chosen to act as a high impedance element between the fourth supply voltage and the I/O pad at relatively high frequency.
18. The integrated circuit of claim 14 , wherein:
a first ESD discharge current is shunted through the first ESD protection circuit and through the first ESD clamp during a positive I/O ESD event;
a second ESD discharge current is shunted through the second ESD protection circuit and through the second ESD clamp during a negative I/O ESD event.
19. The integrated circuit of claim 14 , wherein:
the third supply voltage provides a relatively high reverse bias voltage across a diode of the first ESD protection circuit, thereby reducing a parasitic capacitance of the diode; and
the fourth supply voltage provides a relatively high reverse bias voltage across a diode of the second ESD protection circuit, thereby reducing a parasitic capacitance of the diode.
20. The integrated circuit of claim 14 , further comprising an additional ESD clamp connected in parallel to the internal circuit, between the first voltage supply and the second voltage supply.