Reset in a system-on-chip circuit
View Patent ↗An electronic device having first circuitry operating in a first clock environment and second circuitry operating in a second clock environment, the first circuitry being arranged to generate a soft reset signal for resetting the second circuitry, the integrated circuit further including: a soft reset hold circuit clocked in the first clock environment connected to receive the soft reset signal and to generate an output reset signal in an asserted state; and a synchronizer clocked in the second clock environment connected to receive the output reset signal and to generate a retimed reset signal in an asserted state after a predetermined period, wherein the retimed reset signal is fed back to the soft reset hold circuit to cause the output reset signal to adopt a deasserted state at the end of said predetermined period.
1. An electronic device having first circuitry operating in a first clock environment and second circuitry operating in a second clock environment, the first circuitry being arranged to generate a soft reset signal for resetting the second circuitry, the integrated circuit further comprising:
a soft reset hold circuit clocked in the first clock environment connected to receive the soft reset signal and to generate an output reset signal in an asserted state; and
a synchronizer clocked in the second clock environment connected to receive the output reset signal and to generate a retimed reset signal in an asserted state after a predetermined period,
wherein the retimed reset signal is fed back to the soft reset hold circuit to cause the output reset signal to adopt a deasserted state at the end of said predetermined period.
2. An electronic device according to claim 1 , wherein the soft reset hold circuit comprises a flip-flop and associated logic.
3. An electronic device according to claim 2 , wherein the associated logic comprises an OR gate having as one input the output reset signal of the soft reset hold circuit and an output connected to one input of an AND gate, wherein another input of the AND gate is connected to receive the soft reset signal.
4. An electronic device according to claim 1 , wherein the predetermined time period is related to the second clock environment.
5. An electronic device according to claim 1 , wherein the synchronizer comprises a plurality of serially-connected flip-flops.
6. An electronic device according to claim 5 , wherein the predetermined time period comprises a fixed number of clock cycles of the second clock.
7. An electronic device according to claim 6 , wherein the synchronizer comprises first and second serially connected flip-flops, and the predetermined time period comprises two clock cycles of the second clock.
8. An electronic device according to claim 1 , wherein the first circuitry comprises a CPU.
9. An electronic device according to claim 1 , wherein the soft reset hold circuit and the synchronizer are connected to receive a hard reset signal.
10. An electronic device according to claim 9 , comprising a multiplexer having a first input connected to receive the retimed reset signal and a second input connected to receive the hard reset signal, the multiplexer being controllable by a test signal to selectively connect one of the first and second inputs to an output of the multiplexer.
11. An electronic device according to claim 9 , which comprises a further synchronizer clocked in the first clock environment and connected to receive the hard reset signal and to supply a synchronized reset output signal to the first circuitry.
12. An electronic device according to claim 1 , wherein the second circuitry comprises a CPU.
13. An electronic device according to claim 1 , wherein there is a plurality of second circuitry each with an independent second clock.
14. An electronic device according to claim 1 , comprising an integrated circuit.
15. A system-on-chip comprising an integrated circuit according to claim 14 , and having an input for receiving a data stream and an output for supplying a processed data stream.
16. A system-on-chip according to claim 15 , which comprises a DVD decoder.
17. A system-on-chip according to claim 15 , which comprises a Set Top Box.
18. A DVD player comprising an electronic device according claim 1 .
19. A Set Top Box comprising an electronic device according to claim 1 .
20. A electronic device comprising at least one first chip operating in a first clock environment and at least one second chip operating in a second clock environment, the first chip being arranged to generate a soft reset signal for resetting circuitry of the second chip, the system further comprising:
a soft reset hold circuit clocked in the first clock environment connected to receive the soft reset signal and to generate an output reset signal in an asserted state; and
a synchronizer clocked in the second clock environment connected to receive the output reset signal and to generate a retimed reset signal in an asserted state after a predetermined period,
wherein the retimed reset signal is fed back to the soft reset hold circuit to cause the output reset signal to adopt a deasserted state at the end of said predetermined period.
21. A DVD player comprising an electronic device according to claim 20 .
22. A Set Top Box comprising an electronic device according to claim 20 .
23. A method of transferring a soft reset signal from a first clock environment to a second clock environment, the method comprising:
supplying the soft reset signal to a soft reset hold circuit clocked in the first clock environment, the soft reset hold circuit being arranged to generate an output reset signal in an assertive state;
supplying the output reset signal to a synchronizer clocked in the second clock environment and arranged to generate a retimed reset signal in an assertive state after a predetermined period; and
feeding back the retimed reset signal to the soft reset hold circuit to cause the output reset signal to adopt a deassertive state at the end of said predetermined period.