Voltage level conversion circuit
A voltage level conversion circuit for converting a voltage level of a low voltage system input signal into a voltage level of a high voltage system signal comprises a latch circuit comprising plural high-breakdown-voltage MOS transistors having a high power supply voltage as a breakdown voltage, a first high-breakdown-voltage N channel MOS transistor which discharges one of the latch nodes of the latch circuit, and a second high-breakdown-voltage N channel MOS transistor which discharges the other latch node, and a pulse signal obtained by boosting a low voltage system pulse signal is applied to a gate of the first or second high-breakdown voltage N channel MOS transistor when the input signal transits.
1. A voltage level conversion circuit for converting an input signal having a logical voltage corresponding to a first power supply voltage into an output signal having a logical voltage corresponding to a second power supply voltage that is higher than the first power supply voltage, and outputting the output signal, said voltage level conversion circuit comprising:
a latch circuit comprising plural MOS transistors each having the second power supply voltage as a breakdown voltage, and operable to latch a non-inversion logic corresponding to the input signal at a first latch node while latching an inversion logic reverse to the input signal at a second latch node;
a first N channel MOS transistor having the second power supply voltage as a breakdown voltage, which is connected between the first latch node and a ground voltage supply;
a second N channel MOS transistor having the second power supply voltage as a breakdown voltage, which is connected between the second latch node and the ground voltage supply; and
a transistor driving circuit having the first power supply voltage as a power supply voltage, and operable to apply, when the input signal transits, a pulse signal having a pulse height that is boosted to a level higher than the first power supply voltage, to a gate of the first N channel MOS transistor or to a gate of the second N channel MOS transistor;
a third N channel MOS transistor having the first power supply voltage as a breakdown voltage, which is connected in series to the first N channel MOS transistor, between the first latch node and the ground voltage supply; and
a fourth N channel MOS transistor having the first power supply voltage as a breakdown voltage, which is connected in series to the second N channel MOS transistor, between the second latch node and the ground voltage supply.
2. A voltage level conversion circuit as defined in claim 1 wherein
when the input signal transits, said transistor driving circuit is operable to drive both of the first and third N channel MOS transistors or to drive both of the second and fourth N channel MOS transistors using the pulse signal.
3. A voltage level conversion circuit as defined in claim 1 wherein
said transistor driving circuit maintains the off states of the first to fourth N channel MOS transistor so that the output signal is not reset to the logic corresponding to the input signal, when the voltage level conversion circuit is powered on.
4. A voltage level conversion circuit as defined in claim 1 wherein
said transistor driving circuit drives the first to fourth N channel MOS transistors so that the output signal is reset to the logical voltage corresponding to the input signal, when the voltage level conversion circuit is powered on.
5. A voltage level conversion circuit as defined in claim 1 wherein
when the input signal transits, said transistor driving circuit is operable to apply a pulse signal whose pulse height is boosted to a level higher than the first power supply voltage to the gate of the first N channel MOS transistor or to the gate of the second N channel MOS transistor, and to apply a logical signal according to the input signal or an inversion signal of the input signal to the gate of the third N channel MOS transistor or to the gate of the fourth N channel MOS transistor.
6. A voltage level conversion circuit as defined in claim 4 wherein
said transistor driving circuit maintains the off states of the first to fourth N channel MOS transistors so that the output signal is not reset to the logical voltage corresponding to the input signal, when the voltage level conversion circuit is powered on.
7. A voltage level conversion circuit as defined in claim 4 wherein
said transistor driving circuit drives the first to fourth N channel MOS transistors so that the output signal is reset to the logical voltage corresponding to the input signal, when the voltage level conversion circuit is powered on.
8. A voltage level conversion circuit for converting an input signal having a logical voltage corresponding to a first power supply voltage into an output signal having a logical voltage corresponding to a second power supply voltage that is higher than the first power supply voltage, and outputting the output signal said voltage level conversion circuit comprising:
a latch circuit comprising plural MOS transistors each having the second power supply voltage as a breakdown voltage, and operable to latch a non-inversion logic corresponding to the input signal at a first latch node while latching an inversion logic reverse to the input signal at a second latch node;
a first N channel MOS transistor having the second power supply voltage as a breakdown voltage, which is connected between the first latch node and a ground voltage supply;
a second N channel MOS transistor having the second power supply voltage as a breakdown voltage, which is connected between the second latch node and the ground voltage supply; and
a transistor driving circuit having the first power supply voltage as a power supply voltage, and operable to apply, when the input signal transits, a pulse signal having a pulse height that is boosted to a level higher than the first power supply voltage, to a gate of the first N channel MOS transistor or to a gate of the second N channel MOS transistor;
wherein, when the input signal transits, a pulse signal whose pulse height varies from the ground voltage to a boosted voltage higher than the first power supply voltage is applied to the gate of the first N channel MOS transistor or to the gate of the second N channel MOS transistor.
9. A voltage level conversion circuit as defined in claim 7 wherein
said transistor driving circuit maintains the off states of the first and second N channel MOS transistors so that the output signal is not reset to the logical voltage corresponding to the input signal, when the voltage level conversion circuit is powered on.
10. A voltage level conversion circuit as defined in claim 7 wherein
said transistor driving circuit drives the first and second N channel MOS transistors so that the output signal is reset to the logical voltage corresponding to the input signal, when the voltage level conversion circuit is powered on.
11. A voltage level conversion circuit for converting an input signal having a logical voltage corresponding to a first power supply voltage into an output signal having a logical voltage corresponding to a second power supply voltage that is higher than the first power supply voltage, and outputting the output signal, said voltage level conversion circuit comprising:
a latch circuit comprising plural MOS transistors each having the second power supply voltage as a breakdown voltage, and operable to latch a non-inversion logic corresponding to the input signal at a first latch node while latching an inversion logic reverse to the input signal at a second latch node;
a first N channel MOS transistor having the second power supply voltage as a breakdown voltage, which is connected between the first latch node and a ground voltage supply;
a second N channel MOS transistor having the second power supply voltage as a breakdown voltage, which is connected between the second latch node and the ground voltage supply; and
a transistor driving circuit having the first power supply voltage as a power supply voltage, and operable to apply, when the input signal transits, a pulse signal having a pulse height that is boosted to a level higher than the first power supply voltage, to a gate of the first N channel MOS transistor or to a gate of the second N channel MOS transistor;
said latch circuit comprising:
a first series circuit comprising a P channel MOS transistor having the second power supply voltage as a breakdown voltage and an N channel MOS transistor having the second power supply voltage as a breakdown voltage, which are connected in series between the second power supply and the ground voltage supply; and
a second series circuit comprising a P channel MOS transistor having the second power supply voltage as a breakdown voltage and an N channel MOS transistor having the second power supply voltage as a breakdown voltage, which are connected in series between the second power supply and the ground voltage supply;
wherein the first latch node is a connection point of the power supply side P channel MOS transistor and the ground side N channel MOS transistor in the first series circuit which is connected to gates of the P channel MOS transistor and the N channel MOS transistor in the second series circuit; and
wherein the second latch node is a connection point of the power supply side P channel MOS transistor and the ground side N channel MOS transistor in the second series circuit which is connected to gates of the P channel MOS transistor and the N channel MOS transistor in the first series circuit.
12. A voltage level conversion circuit for converting an input signal having a logical voltage corresponding to a first power supply voltage into an output signal having a logical voltage corresponding to a second power supply voltage that is higher than the first power supply voltage, and outputting the output signal, said voltage level conversion circuit comprising:
a latch circuit comprising plural MOS transistors each having the second power supply voltage as a breakdown voltage, and operable to latch a non-inversion logic corresponding to the input signal at a first latch node while latching an inversion logic reverse to the input signal at a second latch node;
a first N channel MOS transistor having the second power supply voltage as a breakdown voltage, which is connected between the first latch node and a ground voltage supply;
a second N channel MOS transistor having the second power supply voltage as a breakdown voltage which is connected between the second latch node and the ground voltage supply; and
a transistor driving circuit having the first power supply voltage as a power supply voltage, and operable to apply, when the input signal transits, a pulse signal having a pulse height that is boosted to a level higher than the first power supply voltage, to a gate of the first N channel MOS transistor or to a gate of the second N channel MOS transistor;
said latch circuit comprising:
a first series circuit comprising two P channel MOS transistors having the second power supply voltage as a breakdown voltage, which are connected in series between the second power supply and the first latch node, and an N channel MOS transistor having the second power supply voltage as a breakdown voltage, which is connected between the first latch node and the ground voltage supply; and
a second series circuit comprising two P channel MOS transistors having the second power supply voltage as a breakdown voltage, which are connected in series between the second power supply and the second latch node, and an N channel MOS transistor having the second power supply voltage as a breakdown voltage, which is connected between the second latch node and the ground voltage supply; wherein:
a gate of the power supply side P channel MOS transistor in the first series circuit and a gate of the N channel MOS transistor in the first series circuit are connected to the second latch node;
a gate of the power supply side P channel MOS transistor in the second series circuit and a gate of the N channel MOS transistor in the second series circuit are connected to the first latch node; and
a pulse signal which is generated in the transistor driving circuit when the input signal transits is applied to gates of the latch node side P channel MOS transistors in the first and second series circuits.
13. A voltage level conversion circuit for converting an input signal having a logical voltage corresponding to a first power supply voltage into an output signal having a logical voltage corresponding to a second power supply voltage that is higher than the first power supply voltage, and outputting the output signal, said voltage level conversion circuit comprising:
a latch circuit comprising plural MOS transistors each having the second power supply voltage as a breakdown voltage, and operable to latch a non-inversion logic corresponding to the input signal at a first latch node while latching an inversion logic reverse to the input signal at a second latch node;
a first N channel MOS transistor having the second power supply voltage as a breakdown voltage, which is connected between the first latch node and a ground voltage supply;
a second N channel MOS transistor having the second power supply voltage as a breakdown voltage, which is connected between the second latch node and the ground voltage supply; and
a transistor driving circuit having the first power supply voltage as a power supply voltage, and operable to apply, when the input signal transits, a pulse signal having a pulse height that is boosted to a level higher than the first power supply voltage, to a gate of the first N channel MOS transistor or to a gate of the second N channel MOS transistor;
said latch circuit comprising:
a first P channel MOS transistor having the second power supply voltage as a breakdown voltage, which is connected between the second power supply and the first latch node; and
a second P channel MOS transistor having the second power supply voltage as a breakdown voltage, which is connected between the second power supply and the second latch node;
wherein a gate of the first P channel MOS transistor is the second latch node, and a gate of the second P channel MOS transistor is the first latch node.