Methods and apparatus for reducing a sampling rate during a sampling phase determination process
View Patent ↗A received signal is sampled at a sampling period of T+m*(T/n) during a sampling phase determination process. T is a symbol or chip period of the received signal, n is a number of phases of the sampled signal, T/n is a phase resolution period, and m is a fixed non-zero integer value where −n<m<n (e.g. m=1 or −1). By sampling the received signal at the sampling period of T+m*(T/n), a sample set for each one of n phases of the sampled signal is produced. For each sample set, a correlation process is performed between the sample set and a predetermined correlation signal to produce a correlation result. Once an optimal correlation result is identified from the correlation process, the received signal is sampled at a sampling period of T at a phase associated with the optimal correlation result. Advantageously, oversampling at a sampling rate of n/T is not required during the sampling phase determination process, which reduces cost and power consumption.
1. A method for use in a receiver, the method comprising the acts of:
sampling, in the receiver, a signal at a sampling period of T+m*(T/n) for producing a sample set for each one of n phases of the sampled signal, where T is a symbol or chip period of the signal, n is a number of phases of the sampled signal where n≧4, and m is a non-zero integer value where −n<m<n;
for each sample set, performing a correlation process between the sample set and a predetermined correlation signal for producing a correlation result; and
sampling, in the receiver, the received signal at a sampling period of T at a phase associated with an optimal correlation result.
2. The method of claim 1 , where m=+/−1.
3. The method of claim 1 , where n is an integer value between 4-20.
4. The method of claim 1 , further comprising:
wherein the act of sampling the signal at the sampling period of T+m*(T/n) comprises sampling the received signal during a first time period; and
wherein the act of sampling the signal at the sampling period of T comprises sampling during a second time period following the first time period.
5. The method of claim 1 , further comprising:
wherein the act of sampling the signal at the sampling period of T+m*(T/n) comprises sampling a signal comprising a predetermined code; and
wherein the act of sampling the signal at the sampling period of T comprises sampling a signal comprising a user or signaling information.
6. The method of claim 1 , further comprising:
wherein the act of sampling the signal at the sampling period of T+m*(T/n) comprises sampling with a first analog-to-digital converter; and
wherein the act of sampling the signal at the sampling period of T comprises sampling with use of a second analog-to-digital converter.
7. The method of claim 1 , wherein the predetermined correlation signal comprises a pseudorandom noise (PN) sequence.
8. The method of claim 1 , wherein n=4, 8, or 16.
9. The method of claim 1 , further comprising:
performing a first downsampling process to produce the sample set for each one of n phases of the sampled signal; and
performing a second downsampling process to produce the predetermined correlation signal for each correlation process associated with the sample sets.
10. An electronic circuit comprising:
control circuitry;
an analog-to-digital converter which includes a sampler;
the control circuitry being adapted to cause the sampler to sample a received signal at a sampling period of T+m*(T/n) during a sampling phase determination process, where T is a symbol or chip period of the signal, n is the number of phases of the sampled signal where n≧4, T/n is a phase resolution period, and m is a non-zero integer value where −n <m<n;
an output from the sampler which provides a sample set for each one of n phases of the sampled signal during the sampling phase determination process;
a plurality of n correlators, each correlator having:
a first input adapted to receive one of the sample sets associated with a corresponding one of the n phases of the sampled signal;
a second input adapted to receive a predetermined correlation signal;
an output which provides a correlation result from a correlation process between the sample set and the predetermined correlation signal; and
the control circuitry being further adapted to cause the sampler to sample the received signal at a sampling period of T at one of the n phases associated with an optimal correlation result.
11. The electronic circuit of claim 10 , where m=+/−1.
12. The electronic circuit of claim 10 , where n is an integer between 4-20.
13. The electronic circuit of claim 10 , wherein the control circuitry is further adapted to cause the sampler to sample the received signal at the sampling period of T+m*(T/n) during a first time period and at the sampling period of T during a second time period following the first time period.
14. The electronic circuit of claim 10 , wherein the control circuitry is further adapted to cause the sampler to sample a received signal comprising a predetermined code at the sampling period of T+m*(T/n) and to sample a received signal comprising user or signaling information at the sampling period of T.
15. The electronic circuit of claim 10 , further comprising:
a pseudorandom noise (PN) generator which produces the predetermined correlation signal comprising a PN signal.
16. The electronic circuit of claim 10 , wherein n=4, 8, or 16.
17. The electronic circuit of claim 10 , further comprising:
a first plurality of n downsamplers coupled to the output from the sampler to produce the sample set for each one of n phases of the sampled signal; and
a second plurality of n downsamplers to produce the predetermined correlation signal for each one of the plurality of n correlators.
18. A communication device, comprising:
a wireless receiver;
a frequency synthesizer of the wireless receiver;
control circuitry coupled to the frequency synthesizer;
an analog-to-digital converter which includes:
a sampler;
an input for receiving a signal through the wireless receiver;
a clock input coupled to a clock output of the frequency synthesizer;
the control circuitry being adapted to set the frequency synthesizer to produce a clock signal at the clock output so that the sampler samples the received signal at a sampling period of T+m*(T/n) during a sampling phase determination process, where T is a symbol or chip period of the signal, n is the number of phases of the sampled signal where n≧4, T/n is a phase resolution period, and m is a non-zero integer value where −n<m <n;
an output from the analog-to-digital converter providing a sample set for each one of n phases of the sampled signal during the sampling phase determination process;
a plurality of n correlators, each correlator having:
a first input adapted to receive one of the sample sets associated with a corresponding one of the n phases of the sampled signal;
a second input adapted to receive a predetermined correlation signal;
an output which provides a correlation result from a correlation process between the sample set and the predetermined correlation signal; and
the control circuitry being adapted to set the frequency synthesizer to produce a clock signal at the clock output so that the sampler samples the received signal at a sampling period of T at one of n phases associated with an optimal correlation result.
19. The communication device of claim 18 , where m=+/−1.
20. The communication device of claim 18 , wherein the sampler is set to sample the received signal at the sampling period of T+m*(T/n) during a first time period and set to sample the received signal at the sampling period of T during a second time period following the first time period.
21. The communication device of claim 18 , wherein the sampler is set to sample a received signal comprising a synchronization or preamble signal at the sampling period of T+m*(T/n) and set to sample a received signal comprising a user or signaling information at the sampling period of T.
22. The communication device of claim 18 , further comprising:
a first plurality of n downsamplers coupled to the output from the analog-to-digital converter to produce the sample set for each one of n phases of the sampled signal; and
a second plurality of n downsamplers to produce the predetermined correlation signal for each one of the plurality of n correlators.