IP Library Granted Patent US 7,663,191
Granted Patent B2
US 7,663,191 · App. 11/178,612 · Granted Feb 16, 2010

Semiconductor device and manufacturing method thereof with rounded gate including a silicide on the top and at the corners

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Quick Facts
Patent No.
US 7,663,191
App. No.
11/178,612
Granted
Feb 16, 2010
Kind
B2
Abstract

In order that a top surface of a gate electrode does not have sharp portions, ends of the top surface of the gate electrode are rounded before refractory metal is deposited for silicidation. This reduces intensive application of film stresses which are generated in heat treatment, enabling formation of a silicide layer with a uniform, sufficient thickness.

Claims (38)

1. A semiconductor device, comprising:

a substrate; and

a first gate electrode formed on the substrate and extending in a prescribed direction, wherein

the first gate electrode has a first silicide layer at its top surface, and

a bottom surface of the first silicide layer has an approximately circular arc shape downward from a side end of the first silicide layer toward the center direction and a top surface of the first silicide layer has an approximately circular arc shape upward from a side end of the first silicide layer toward the center direction.

2. The semiconductor device according to claim 1 , wherein a first sidewall is formed on a side surface of the first gate electrode, and a distance between the top surface of the first gate electrode and a top end of the first sidewall is 0 nm to 50 nm.

3. The semiconductor device according to claim 1 , comprising the first gate electrode and a second gate electrode respectively formed on the substrate and extending in the prescribed direction,

wherein the first gate electrode has the first silicide layer on the top surface thereof and the second gate electrode has a second silicide layer on the top surface thereof, and

the first gate electrode has an electrode width of less than 150 nm and the second gate electrode has an electrode width of more than 500 nm.

4. The semiconductor device according to claim 1 , wherein the first silicide layer is formed from two layers.

5. The semiconductor device according to claim 1 , wherein center portions of the top and bottom surface of the first silicide layer have an upward approximately circular arc shape.

6. A semiconductor device, comprising:

a substrate; and

a first gate electrode formed on the substrate and extending in a prescribed direction, wherein

the first gate electrode has a first polysilicon layer and a first silicide layer formed on the first polysilicon layer, and

a top surface of the first polysilicon layer has a circular shape downward from a side end of the first polysilicon layer toward the center direction.

7. The semiconductor device according to claim 6 , wherein the center portion of the top surface of the first polysilicon layer has an upward approximately circular arc shape.

8. The semiconductor device according to claim 6 , wherein

a bottom surface of the first silicide layer has an approximately circular arc shape downward from a side end of the first silicide layer toward the center direction, and

a top surface of the first silicide layer has an approximately circular arc shape upward from a side end of the first silicide layer toward the center direction.

9. The semiconductor device according to claim 6 , wherein center portions of the top and bottom surface of the first silicide layer have an upward approximately circular arc shape.

10. The semiconductor device according to claim 6 , wherein

a first sidewall is formed on a side surface of the first gate electrode, and a distance between the top surface of the first gate electrode and a top end of the first sidewall is 0 nm to 50 nm.

11. The semiconductor device according to claim 6 , wherein the first silicide layer is formed from two layers.

12. The semiconductor device according to claim 3 , wherein

a first sidewall is formed on a side surface of the first gate electrode, and

in the first silicide layer of the first gate electrode which is present in a boundary region with the first sidewall, a thickness of the first silicide layer located below the top end of the first sidewall is 40% or more of a thickness of the second silicide layer in a middle of the second gate electrode in a width direction.

13. The semiconductor device according to claim 3 , wherein

a bottom surface of the second silicide layer has an approximately circular arc shape downward from a side end of the second silicide layer toward the center direction, and

a top surface of the second silicide layer has an approximately circular arc shape upward from a side end of the second silicide layer toward the center direction.

14. The semiconductor device according to claim 3 , wherein center portions of the top and bottom surface of the first silicide layer have an upward approximately circular arc shape.

15. The semiconductor device according to claim 3 , wherein

the second gate electrode has a second polysilicon layer and a second silicide layer formed on the second polysilicon layer, and

a top surface of the second polysilicon layer has an approximately circular arc shape downward from a side end of the second polysilicon layer toward the center direction.

16. The semiconductor device according to claim 3 , wherein

a second sidewall is formed on a side surface of the second gate electrode, and a distance between the top surface of the second gate electrode and a top end of the second sidewall is 0 nm to 50 nm.

17. The semiconductor device according to claim 1 , wherein the first silicide layer has an approximately same thickness at the side end and in the middle.

18. The semiconductor device according to claim 6 , wherein the first polysilicon layer has a rounded end.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 7, 2015
From: PANASONIC CORPORATION
To: PANNOVA SEMIC, LLC
Reel/Frame 036065/0273 →
CHANGE OF NAME Recorded Nov 24, 2008
From: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
To: PANASONIC CORPORATION
Reel/Frame 021897/0653 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 4, 2005
From: KANEGAE, KENSHI; TSUZUMITANI, AKIHIKO; IKEDA, ATSUSHI
To: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Reel/Frame 016729/0923 →