Node processors for use in parity check decoders
View Patent ↗Techniques for implementing message passing decoders, e.g., LDPC decoders, are described. To facilitate hardware implementation messages are quantized to integer multiples of ½ ln2. Messages are transformed between more compact variable and less compact constraint node message representation formats. The variable node message format allows variable node message operations to be performed through simple additions and subtractions while the constraint node representation allows constraint node message processing to be performed through simple additions and subtractions. Variable and constraint nodes are implemented using an accumulator module, subtractor module and delay pipeline. The accumulator module generates an accumulated message sum. The accumulated message sum for a node is stored and then delayed input messages from the delay pipeline are subtracted there from to generate output messages. The delay pipeline includes a variable delay element making it possible to sequentially perform processing operations corresponding to nodes of different degrees.
1. An apparatus, comprising:
means for quantizing a value from a receiver, using quantization step sizes which are integer multiples of ½ In 2, to produce a quantized value; and
means for performing one of a check node processing operation and a variable node processing operation on said quantized value to produce at least a portion of an outgoing message communicating reliability information, said means for performing one of a check node processing operation and a variable node processing operation being coupled to said means for quantizing.
2. The apparatus of claim 1 , wherein said means for quantizing includes:
input means for receiving log-likelihood values, said received value being a log-likelihood value.
3. The apparatus of claim 1 , wherein said means for quantizing includes:
input means for receiving log-likelihood values including at least one of a log-likelihood ratio value and an approximation of a log-likelihood ratio value said received value being a value received by said input means.
4. The apparatus of claim 1 , further comprising:
means for generating said received value by multiplying a detected value with a constant.
5. The apparatus of claim 1 ,wherein said means for quantizing the received value includes:
means for generating a sign bit and a magnitude value which in combination, comprise said quantized value.
6. The apparatus of claim 5 , wherein said means for performing one of a check node and a variable node processing operation includes:
means for shifting a fixed number as a function of the magnitude value included in said quantized value to generate a transformed magnitude value: and
means for performing at least one check node processing operation on said transformed magnitude value to produce an outgoing transformed magnitude value.
7. The apparatus of claim 6 , wherein said means for performing one of a check node and a variable node processing operation includes means for performing a second transform operation to generate a log-likelihood message magnitude value.
8. The apparatus of claim 7 , wherein said means for performing one of a check node and a variable node processing operation further includes means for performing at least one check node processing operation on the sign bit of said quantized value to produce an outgoing sign bit value.
9. The apparatus of claim 8 , wherein said means for performing one of a check node and a variable node processing operation further includes means for combining the outgoing sign bit value with the generated log-likelihood message magnitude value to produce a decoder message including said portion of an output message.
10. The apparatus of claim 9 ,
wherein said means for performing one of a check node processing operation and variable node processing operation is a constraint node processor used to generate said decoder message said decoder message being a constraint node to variable node decoder message.
11. The apparatus of claim 10 , further comprising:
means for storing the constraint node to variable node decoder message in a memory: and
variable node processor means coupled to said memory for generating a variable node to constraint node message as a function of said constraint node to variable node decoder message.