Pixel individual anti-eclipse circuit and its operation manner

1. An imager comprising:

a pixel coupled to a pixel output line; and

a circuit configured to receive and store a pixel reset voltage from said pixel on said pixel output line and configured to use said stored pixel reset voltage as a parameter to control a reset voltage level on said output line in a manner which maintains said pixel reset voltage on said pixel output line above a predetermined minimum voltage, the circuit comprising:

a storage capacitor;

a switch for selectively coupling said output line to said storage capacitor;

a transistor for biasing said output line to control the reset voltage level on said line, a gate of said transistor being coupled to said storage capacitor; and

a switchable voltage source for switchably applying an additional voltage to said capacitor.

2. The imager of claim 1 , wherein said output line is a column line of a pixel array.

3. The imager of claim 1 , wherein said switchable voltage source comprises:

a plurality of voltage source lines; and

a second switch for selectively coupling a selected voltage source line to said capacitor.

4. The imager of claim 3 , wherein said output line further receives a pixel output signal from said pixel and wherein said switch selectively couples a first voltage line having a first voltage higher than said predetermined minimum voltage to said capacitor before said output line receives said pixel output signal.

5. The imager of claim 1 , wherein said transistor is coupled to a voltage supply line and selectively controls application of a voltage from said supply line to said output line in response to voltage on said capacitor.

6. A method of operating an imager comprising the steps of:

receiving and storing a pixel reset voltage from a pixel on an output line and for using said stored pixel reset voltage as a parameter to control a reset voltage level on said output line in a manner which maintains said pixel reset voltage on said pixel output line above a predetermined minimum voltage;

selectively coupling said output line to a storage capacitor;

biasing said output line to control the reset voltage level on said line with a transistor, a gate of said transistor being coupled to said storage capacitor; and

switchably applying an additional voltage to said capacitor with a switchable voltage source.

7. The method of claim 6 , wherein said output line is a column line of a pixel array.

8. The method of claim 6 , further comprising the step of receiving a pixel output signal from said pixel and selectively coupling a first voltage line having a first voltage higher than said predetermined minimum voltage to said capacitor before said output line receives said pixel output signal.

9. An imager array comprising:

a plurality of imager circuits, at least one imager circuit of said plurality comprising:

a pixel coupled to a pixel output line; and

a circuit configured to receive and store a pixel reset voltage from said pixel on said pixel output line and configured to use said stored pixel reset voltage as a parameter to control a reset voltage level on said output line in a manner which maintains said pixel reset voltage on said pixel output line above a predetermined minimum voltage, the circuit comprising:

a storage capacitor;

a switch for selectively coupling said output line to said storage capacitor;

a transistor for biasing said output line to control the reset voltage level on said line, a gate of said transistor being coupled to said storage capacitor; and

a switchable voltage source for switchably applying an additional voltage to said capacitor.

10. The imager array of claim 9 , wherein said output line is a column line of a pixel array.

11. The imager array of claim 9 , wherein said switchable voltage source comprises:

a plurality of voltage source lines; and

a switch for selectively coupling a selected voltage source line to said capacitor.

12. The imager array of claim 11 , wherein said output line further receives a pixel output signal from said pixel and wherein said switch selectively couples a first voltage line having a first voltage higher than said predetermined minimum voltage to said capacitor before said output line receives said pixel output signal.

13. The imager array of claim 9 , wherein said transistor is coupled to a voltage supply line and selectively controls application of a voltage from said supply line to said output line in response to voltage on said capacitor.

14. A processing system comprising:

a processor; and

an imager array electronically coupled to said processor, said imager array comprising a plurality of imager circuits, at least one imager circuit of said plurality comprising:

a pixel coupled to a pixel output line; and

a circuit configured to receive and store a pixel reset voltage from said pixel on said pixel output line and configured to use said stored pixel reset voltage as a parameter to control a reset voltage level on said output line in a manner which maintains said pixel reset voltage on said pixel output line above a predetermined minimum voltage; the circuit comprising:

a storage capacitor;

a switch for selectively coupling said output line to said storage capacitor;

a transistor for biasing said output line to control the reset voltage level on said line, a gate of said transistor being coupled to said storage capacitor; and

a switchable voltage source for switchably applying an additional voltage to said capacitor.

15. The processing system of claim 14 , wherein said output line is a column line of a pixel array.

16. The processing system of claim 14 , wherein said switchable voltage source comprises:

a plurality of voltage source lines; and

a switch for selectively coupling a selected voltage source line to said capacitor.

17. The processing system of claim 16 , wherein said output line further receives a pixel output signal from said pixel and wherein said switch selectively couples a first voltage line having a first voltage higher than said predetermined minimum voltage to said capacitor before said output line receives said pixel output signal.

18. The processing system of claim 14 , wherein said transistor is coupled to a voltage supply line and selectively controls application of a voltage from said supply line to said output line in response to voltage on said capacitor.

19. A method of forming an imager pixel comprising the steps of:

forming a pixel coupled to a pixel output line; and

forming a circuit for receiving and storing a pixel reset voltage from said pixel on said pixel output line and for using said stored pixel reset voltage as a parameter to control a reset voltage level on said output line in a manner which maintains said pixel reset voltage on said pixel output line above a predetermined minimum voltage; wherein forming the circuit comprises:

forming a storage capacitor;

forming a switch for selectively coupling said output line to said storage capacitor;

forming a transistor for biasing said output line to control a reset voltage level on said line, a gate of said transistor being coupled to said storage capacitor; and

forming a switchable voltage source for switchably applying an additional voltage to said capacitor.

20. The method of claim 19 , wherein said step of forming a circuit further comprises forming said output line as a column line of a pixel array.

21. The method of claim 19 , wherein said step of forming the switchable voltage source comprises:

forming a plurality of voltage source lines; and

forming a switch for selectively coupling a selected voltage source line to said capacitor.

22. The method of claim 21 , wherein said output line is formed to receive a pixel output signal from said pixel and wherein said switch is formed to selectively couple a first voltage line having a first voltage higher than said predetermined minimum voltage to said capacitor before said output line receives said pixel output signal.

23. The method of claim 19 , wherein said step of forming the transistor further comprises forming said transistor to be coupled to a voltage supply line and to selectively control application of a voltage from said supply line to said output line in response to voltage on said capacitor.

24. An imager comprising:

a pixel for supplying a pixel reset voltage; and

a circuit configured to monitor said pixel reset voltage and configured to produce in response to said monitored pixel reset voltage a voltage on the line which has a waveform which starts at a nominal voltage, then increases to maintain a differential above a predetermined minimum voltage until an output of said pixel is read out, the circuit comprising:

a storage capacitor;

a switch for selectively coupling said output line to said storage capacitor;

a transistor for biasing said output line to control the reset voltage level on said line, a gate of said transistor being coupled to said storage capacitor; and

a switchable voltage source for switchably applying an additional voltage to said capacitor.