IP Library Granted Patent US 7,218,084
Granted Patent B2
US 7,218,084 · App. 11/179,782 · Granted May 15, 2007

Integrated circuit with modulable low dropout voltage regulator

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Quick Facts
Patent No.
US 7,218,084
App. No.
11/179,782
Granted
May 15, 2007
Kind
B2
Abstract

A low dropout voltage (LDO) regulator comprises an output stage (EtS) of the amplifier (AMP), which has a main output and n auxiliary outputs which can respectively deliver a main control voltage (V GPRINC ) and n auxiliary control voltages (V G1 , . . . , V Gn ); and a power stage (EtP) which has a main power transistor (PmosPrinc), controlled at its gate by the main control voltage (V GPRINC ), and p power modules (module 1 , . . . , module n) of identical layout with p less than or equal to n, respectively having p auxiliary power transistors (PMos 1 , . . . , PMosn) each controlled at their gate by p auxiliary control voltages (V G1 , . . . , V Gn ). The number p is selected as a function of an intended maximum output current.

Claims (42)

1. An integrated circuit comprising:

a low dropout voltage (LDO) regulator, the LDO regulator including:

an operational amplifier, wherein the amplifier includes an output stage and a power stage, wherein the output stage includes a main output and up to n auxiliary outputs, wherein the main output deliverers a main control voltage and each of the n auxiliary outputs delivers at least one of n auxiliary control voltages, where n is a positive integer; and

wherein the power stage which is fed back to the operational amplifier and delivers an output current when coupled to a load, wherein the power stage has a main power transistor with a gate controlled by the main control voltage, and up to p power modules of identical layout with a number p less than or equal to a number n, and wherein each of the p power modules have an auxiliary power transistor with a gate controlled by one of the n auxiliary control voltages, where p is a positive integer.

2. The integrated circuit of claim 1 , wherein the number p is selected as a function of an intended maximum output current.

3. The integrated circuit of claim 1 , wherein the output stage includes:

a main output transistor and up to n identical auxiliary output transistors, wherein that a main internal impedance is connected between a supply voltage and the main output transistor;

wherein up to n identical auxiliary internal impedances belonging to the power stage are respectively connected between the supply voltage and each of n auxiliary output transistors.

4. The integrated circuit of claim 3 , wherein the LDO regulator is formed in two parts, a first part including the operational amplifier with the output stage and a second part including the n identical auxiliary internal impedances and the main power transistor and the p power modules of identical layout,

wherein the layout of each the p power modules incorporating each of the n identical auxiliary internal impedances for electrically connecting with the n auxiliary output transistors which can deliver the control voltage to the n identical auxiliary output transistors contained in the p power modules.

5. The integrated circuit of claim 4 , wherein the second part of the LDO regulator is formed in two sub-parts, a first sub-part including the n identical auxiliary internal impedances and a second sub-part including the main power transistor and the p power modules of identical layout.

6. The integrated circuit of claim 4 , wherein physical dimensions of the main power transistor are less than physical dimensions of each of the p auxiliary power transistors.

7. The integrated circuit of claim 4 , wherein physical dimensions of the main power transistor are less than physical dimensions of each of the n auxiliary transistors.

8. The integrated circuit of claim 4 , wherein the auxiliary power transistors has a cut off frequency Fc characterized by:

Fc

=

1

2

*

π

*

Z

int

ernei

*

Cg

PMOSi

,

where CgPMosi representing a stray capacitance for each auxiliary power transistor and

wherein Zint ernie is each of the n internal auxiliary internal impedances.

9. The integrated circuit of claim 8 , wherein Fc is identical for each auxiliary power transistor and independent of n.

10. A low dropout voltage regulator, the regulator comprising:

an operational amplifier, wherein the amplifier includes an output stage and a power stage, wherein the output stage includes a main output and up to n auxiliary outputs, wherein the main output deliverers a main control voltage and each of the n auxiliary outputs delivers at least one of n auxiliary control voltages, where n is a positive integer; and

wherein the power stage which is fed back to the operational amplifier and delivers an output current when coupled to a load, wherein the power stage has a main power transistor with a gate controlled by the main control voltage, and up to p power modules of identical layout with a number p less than or equal to a number n, and wherein each of the p power modules have an auxiliary power transistor with a gate controlled by one of the n auxiliary control voltages, where p is a positive integer.

11. The low dropout voltage regulator of claim 10 , wherein the number p is selected as a function of an intended maximum output current.

12. The low dropout voltage regulator of claim 10 , wherein the output stage includes:

a main output transistor and up to n identical auxiliary output transistors, wherein that a main internal impedance is connected between a supply voltage and the main output transistor;

wherein up to n identical auxiliary internal impedances belonging to the power stage are respectively connected between the supply voltage and each of n auxiliary output transistors.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 16, 2014
From: ST-ERICSSON SA
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 033753/0921 →
CHANGE OF NAME Recorded May 15, 2014
From: ST WIRELESS SA
To: ST-ERICSSON SA
Reel/Frame 032908/0765 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 11, 2014
From: STMICROELECTRONICS NV; STMICROELECTRONICS S.A.
To: ST WIRELESS SA
Reel/Frame 032660/0799 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 7, 2005
From: PONS, ALEXANDRE; GRIGIS, FABIENNE
To: STMICROELECTRONICS SA
Reel/Frame 016740/0941 →