Direct channel stress
View Patent ↗An embodiment of the invention provides a semiconductor fabrication method. The method comprises forming a strained channel region in semiconductor devices. Embodiments include forming a stressor layer over an amorphous portion of the semiconductor device at an intermediate stage of fabrication. The device is masked and strain in a portion of the stressor layer is relaxed. Recrystallizing the amorphous portion of the intermediate device transfers strain from the stressor to the substrate. At least a portion of the strain remains in the substrate through subsequent device fabrication, thereby improving performance of the completed device. In other embodiments, a tensile stressor layer is formed over a first portion of the device, and a compressive stressor layer is formed over a second portion. A tensile stressor layer forms a compressive channel in a PMOS device, and a compressive stressor forms a tensile channel in an NMOS device.
1. A method of making a semiconductor device, the method comprising:
forming an amorphous layer over a substrate;
forming a stressor layer over the amorphous layer;
relaxing a stress in a portion of the stressor layer from a first stress to a second stress;
recrystallizing the amorphous layer;
after recrystallizing the amorphous layer, depositing a gate dielectric of a transistor over an upper surface of the substrate; and
depositing a gate electrode over the gate dielectric.
2. The method of claim 1 , wherein forming an amorphous layer comprises converting a surface region of the substrate to the amorphous layer using an ion implant process.
3. The method of claim 2 , wherein the ion implant process comprises implanting germanium at about 1E14 to 1E15 cm-2 at about 20 to 40 keV.
4. The method of claim 1 , wherein the stressor layer comprises silicon nitride.
5. The method of claim 1 , wherein forming the stressor layer comprises a plasma enhanced chemical vapor deposition (PECVD) process.
6. The method of claim 1 , wherein relaxing a stress in a portion of the stressor layer from a first stress to a second stress comprises a germanium ion implant.
7. The method of claim 1 , wherein recrystallizing the amorphous layer comprises a rapid thermal process (RTP) spike anneal at about 1000 to 1100° C. for at least about 1 second.
8. The method of claim 1 , wherein the first stress is tensile and wherein forming a transistor comprises forming an NMOS transistor in the recrystallized amorphous layer.
9. The method of claim 1 , wherein the first stress is compressive and wherein forming a transistor comprises forming a PMOS transistor in the recrystallized amorphous layer.
10. A method of making a semiconductor device, the method comprising:
forming an amorphous layer over a substrate;
forming a first stressor layer over a first portion of the amorphous layer, wherein the first stressor layer has a first intrinsic stress that is one of compressive and tensile;
forming a second stressor layer over a second portion of the amorphous layer, wherein the second stressor layer has a second intrinsic stress that is different than the first intrinsic stress; and
recrystallizing the amorphous layer.
11. The method of claim 10 , wherein the second stress is the other of tensile and compressive.
12. The method of claim 10 , wherein forming the first and second stressor layers comprise a plasma enhanced chemical vapor deposition (PECVD) process.
13. The method of claim 10 , wherein the first and second stressor layers comprise a silicon nitride layer.
14. The method of claim 10 , wherein recrystallizing the amorphous layer comprises a rapid thermal process (RTP) spike anneal at about 1000 to 1100° C. for at least about 1 second.
15. The method of claim 10 , further comprising relaxing at least one of the first intrinsic stress and the second intrinsic stress.
16. A method of making a semiconductor device, the method comprising:
amorphizing an upper surface of a semiconductor body;
forming a layer over the amorphized upper surface;
annealing the upper surface;
after annealing the upper surface, depositing a gate dielectric layer for a transistor over the upper surface; and
depositing a gate electrode layer over the gate dielectric layer.
17. The method of claim 16 , further comprising removing the layer after annealing the upper surface but prior to depositing the gate electrode layer.
18. The method of claim 17 , wherein the layer comprises a stressor layer.
19. The method of claim 18 , wherein amorphizing the upper surface comprises amorphizing the entire upper surface, the method further comprising relaxing a stress in a portion of the stressor layer prior to annealing the upper surface.
20. The method of claim 16 , further comprising etching an isolation trench subsequent to amorphizing the upper surface.
21. The method of claim 16 , wherein amorphizing the upper surface comprises implanting through a material into the upper surface.
22. A method of making a semiconductor device, the method comprising:
amorphizing an upper surface of a semiconductor body;
forming a layer over the amorphized upper surface;
annealing the upper surface; and
after annealing the upper surface, forming doped regions of the semiconductor device.
23. The method of claim 22 , wherein forming doped regions of the semiconductor device comprises forming source/drain regions of a transistor.
24. The method of claim 23 , wherein the following steps are performed in sequence:
amorphizing the upper surface of the semiconductor body;
then forming the layer over the amorphized upper surface;
then annealing the upper surface;
then forming a gate electrode over the upper surface;
then forming lightly doped source/drain regions adjacent the gate electrode;
then forming sidewall spacers along sidewalls of the gate electrode; and
then forming the source/drain regions of the transistor.
25. The method of claim 22 , further comprising removing the layer after annealing the upper surface but prior to forming the doped regions.
26. The method of claim 22 , wherein the layer comprises a stressor layer.
27. The method of claim 22 , wherein amorphizing the upper surface comprises amorphizing the entire upper surface, the method further comprising relaxing a stress in a portion of the stressor layer prior to annealing the upper surface.
28. The method of claim 22 , wherein forming doped regions comprises introducing dopants in the upper surface after annealing the upper surface.
29. The method of claim 28 , wherein forming doped regions comprises implanting ions into the upper surface.