Offset cancel circuit of voltage follower equipped with operational amplifier
View Patent ↗A differential amplifying circuit 11 includes a current mirror circuit having first and second current ends to which drains of MOS transistors M 8 and M 9 are respectively connected, and a pair of differential MOS transistors M 1 and M 2 having gates between which a switch SW 1 is connected. A reference potential Vref is applied to the gate of the MOS transistors M 9 . A switch SW 2 is connected between the output VO of an output buffer circuit 12 and the gate of a MOS transistor M 1 , and a switch SW 3 is connected between the output VO and the gate of the MOS transistor M 8 . During the offset-cancel preparation period, the switches SW 1 and SW 3 are on and the switch SW 2 is off. Next, the switches SW 1 to SW 3 are turned over, consequently outputting offset-canceled potential VO.
1. A data driver for a liquid crystal display device, the data driver including a plurality of voltage followers coupled to a plurality of data lines of the liquid crystal display device, each voltage follower comprising:
a current mirror circuit having first and second current ends as a pair of differential potential outputs;
a first differential input circuit including first and second transistors, the first transistor having a current-path whose one end is connected to the first current end and having a gate, the second transistor having a current-path whose one end is connected to the second current end and having a gate receiving a input signal;
an output buffer circuit having an output for providing a signal according to a potential at the second current end, the output being coupled to one of the plurality of data lines;
a second differential input circuit including third and fourth transistors, the third transistor having a current-path whose one end is connected to the first current end and having a gate, the fourth transistor having a current-path whose one end is connected to the second current end and having a gate receiving a reference potential;
a first switch connected between the gate of the first transistor and the gate of the second transistor;
a second switch connected between the output and the gate of the first transistor, the second switch being on/off-controlled adversely to the first switch;
a third switch connected between the output and the gate of the third transistor, the third switch being on/off-controlled in gang with the first switch; and
a capacitor connected between the gate of the third transistor and a predetermined potential.
2. The data driver according to claim 1 , wherein the first differential input circuit further comprises:
a constant current source;
a first diode, connected between the constant current source and another end of the current-path of the first transistor, for preventing a backflow; and
a second diode, connected between the constant current source and another end of the current-path of the second transistor, for preventing a backflow.
3. The data driver according to claim 1 , wherein the predetermined potential is equal to the reference potential.
4. The data driver according to claim 1 , wherein the reference potential is substantially equal to a central potential in an operation range of an input signal provided to the non-inverting input.
5. The data driver according to claim 1 , wherein the reference potential is substantially equal to a mean value of a maximum value and a minimum value in a gray-scale potential range of a liquid crystal display panel.
6. A liquid crystal display device, comprising:
a liquid crystal display panel including a plurality of data lines; and
the data driver including a plurality of voltage followers coupled to the plurality of data lines,
wherein each voltage follower comprises:
a current mirror circuit having first and second current ends as a pair of differential potential outputs;
a first differential input circuit including first and second transistors, the first transistor having a current-path whose one end is connected to the first current end and having a gate, the second transistor having a current-path whose one end is connected to the second current end and having a gate receiving a input signal;
an output buffer circuit having an output for providing a signal according to a potential at the second current end, the output being coupled to one of the plurality of data lines;
a second differential input circuit including third and fourth transistors, the third transistor having a current-path whose one end is connected to the first current end and having a gate, the fourth transistor having a current-path whose one end is connected to the second current end and having a gate receiving a reference potential;
a first switch connected between the gate of the first transistor and the gate of the second transistor;
a second switch connected between the output and the gate of the first transistor, the second switch being on/off-controlled adversely to the first switch;
a third switch connected between the output and the gate of the third transistor, the third switch being on/off-controlled in gang with the first switch; and
a capacitor connected between the gate of the third transistor and a predetermined potential.