IP Library Granted Patent US 7,058,273
Granted Patent B1
US 7,058,273 · App. 11/182,662 · Granted Jun 6, 2006

Polysilicon light scatterers for silicon waveguides on five layer substrates

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Quick Facts
Patent No.
US 7,058,273
App. No.
11/182,662
Granted
Jun 6, 2006
Kind
B1
Abstract

In a standard CMOS process, a layer of metallic salicide can be deposited on those selected portions of an integrated circuit, where it is desired to have metallic contacts for electronic components, such as transistors. The deposition of a salicide into optical elements such as the core of an optical waveguide or a light scatterer will damage the elements and prevent the passage of light through those sections of the elements. Prior to the deposition of the salicide, a salicide blocking layer is deposited on those parts of an integrated circuit, such as on an optical waveguide or a light scatterer, which are to be protected from damage by the deposition of salicide. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide and a light scatterer.

Claims (33)

1. A light scattering element for an optical waveguide with a core, where the core of the optical waveguide is comprised of:

a layer of monocrystalline silicon,

a layer of dielectric material disposed on the layer of monocrystalline silicon, and

a strip of monocrystalline silicon disposed on the layer of dielectric material, where the strip and a silicon body of a transistor are formed from the same monocrystalline silicon on the same substrate,

and

the light scattering element is comprised of:

a layer of polysilicon disposed on the strip of monocrystalline silicon, where the layer of polysilicon and a polysilicon gate for a transistor are formed at the same time from the same polysilicon, and

a cladding comprised of a plurality of dielectric materials,

where the cladding is disposed over:

the core and

the layer of polysilicon, and

where at least one of the plurality of dielectric materials is comprised of a layer of salicide block used during the fabrication of a transistor.

2. The optical waveguide of claim 1 , wherein the substrate is comprised of a layer of silicon dioxide disposed on a layer of monocrystalline silicon.

3. The optical waveguide of claim 2 , wherein

the substrate,

a slab of monocrystalline silicon disposed on the substrate,

the layer of dielectric material disposed on the slab of monocrystalline silicon and

a layer of monocrystalline silicon disposed on the layer of dielectric material, where the strip of monocrystalline silicon is formed from the layer of monocrystalline silicon,

comprises a wafer.

4. The optical waveguide of claim 1 , wherein the layer of dielectric material is comprised of silicon dioxide and is used to electrically isolate the transistor from the slab of monocrystalline silicon.

5. The light scattering element of claim 1 , wherein the cladding includes a bottom cladding comprised of a top layer of the substrate.

6. The light scattering element of claim 1 , wherein the cladding includes a layer of dielectric material formed at the same time as a sidewall passivation for the silicon body of a transistor.

7. The light scattering element of claim 1 , wherein the cladding includes a plurality of layers of dielectric material formed at the same time as a plurality of dielectric materials used as a gate spacer for a transistor.

8. The light scattering element of claim 1 , wherein the cladding includes a layer of dielectric material formed at the same time as a contact punch-through layer for a transistor.

9. The light scattering element of claim 1 , wherein the cladding includes a layer of dielectric material formed at the same time as an inter-level dielectric for a transistor.

10. The light scattering element of claim 6 , 7 , 8 or 9 , wherein the layer of dielectric material included in the cladding is selected from the group comprising: silicon dioxide, silicon oxynitride and silicon nitride.

11. The light scattering element of claim 1 , wherein at least one of the plurality of dielectric materials is selected from a group of dielectrics used at the same time to form a dielectric element of a transistor,

where the group of dielectrics comprises: a contact punch-through layer, an inter-layer dielectric film, a gate spacer, a salicide block, a dielectric spacer, a sidewall passivation film, an isolation dielectric, an oxide spacer and a field oxide.

12. The light scattering element of claim 11 , wherein thermal oxidation is used to form a sidewall passivation film,

where the sidewall passivation film is used as one of a plurality of dielectric materials for the optical waveguide and is formed at the same time as the sidewall passivation film for the body of a transistor.

13. The light scattering element of claim 1 , wherein at least one of the plurality of dielectric materials is selected from the group comprising: SiO 2 , SiCOH, SiCOF, Si 3 N 4 , SiON, BPSG and silicon-based materials including one or more of the following elements: oxygen, carbon, nitrogen, hydrogen, boron, phosphorus, fluorine and arsenic.

14. The light scattering element of claim 1 , wherein the transistor is selected from the group comprising: a CMOS transistor, a BiCMOS transistor, a bipolar junction transistor (BJT) and a junction FET (JFET) transistor.

15. The light scattering element of claim 1 , wherein the salicide block layer is used as a gate spacer during the fabrication of a transistor on the same substrate.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNOR'S NAME PREVIOUSLY RECORDED AT REEL: 058979 FRAME: 0027. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 24, 2022
From: LUXTERA LLC
To: CISCO TECHNOLOGY, INC.
Reel/Frame 059496/0803 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 8, 2022
From: CISCO SYSTEMS, INC.
To: CISCO TECHNOLOGY, INC.
Reel/Frame 058979/0027 →
RELEASE OF SECURITY INTEREST Recorded Dec 24, 2020
From: SILICON VALLEY BANK
To: LUXTERA, LLC
Reel/Frame 054855/0838 →
CHANGE OF NAME Recorded Feb 6, 2020
From: LUXTERA, INC.
To: LUXTERA LLC
Reel/Frame 052019/0811 →
SECURITY INTEREST Recorded Mar 29, 2017
From: LUXTERA, INC.
To: SILICON VALLEY BANK
Reel/Frame 042109/0140 →
SECURITY AGREEMENT Recorded Jun 17, 2009
From: LUXTERA, INC.
To: SILICON VALLEY BANK
Reel/Frame 022835/0340 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2005
From: GUNN III, LAWRENCE C.; PINGUET, THIERRY J.; RATTIER, MAXIME JEAN
To: LUXTERA, INC
Reel/Frame 016788/0105 →