High speed packet-buffering system
A number of techniques for implementing packet-buffering memory systems and packet-buffering memory architectures are disclosed. In one embodiment, a packet-buffering memory system comprises a high-latency memory sub system with a latency time of L and a low-latency memory subsystem. The low-latency memory subsystem contains enough memory to store an amount of packet data to last L seconds when accessed from low-latency memory subsystem at an access-rate of A. The packet-buffering system further comprises a FIFO controller that responds to a packet read request by simultaneously requesting packet data from said high-latency memory subsystem while simultaneously requesting and quickly responding with packet data obtained from the low-latency memory subsystem.
1 . A First-In First-Out (FIFO) memory subsystem for providing FIFO memory services at a guaranteed minimum rate, said FIFO memory system comprising:
a high-latency memory system, said high-latency memory system having a latency of L H seconds;
a low-latency memory system, said low-latency memory having a latency of L L , said low-latency memory system storing at least enough data to last L L -L H seconds at said guaranteed minimum rate; and
a FIFO memory controller, said FIFO memory controller responding to a read request by initiating a request for data from said high-latency memory system while immediately responding with data from said low-latency system.
2 . The First-In First-Out (FIFO) memory subsystem of claim 1 wherein said high-latency memory system has a memory bandwidth sufficient to handle sustained FIFO requests at said guaranteed minimum rate.
3 . The First-In First-Out (FIFO) memory subsystem of claim 1 wherein said FIFO memory system stores network packets.
4 . The First-In First-Out (FIFO) memory subsystem of claim 1 wherein said high-latency memory system comprises embedded DRAM.
5 . A pipelined memory subsystem, said pipelined memory system comprising:
a high-latency memory system, said high-latency memory system having a latency of L and an access-rate of A;
a pipelined memory controller, said pipelined controller responding to a read request by requesting data from said high-latency memory system while immediately responding with data from a previous read request, said pipelined memory controller responding to said read request within said latency L.
6 . The pipelined memory subsystem of claim 5 further comprising:
a low-latency memory system, said low-latency memory system having an access-rate of at least A;
7 . The pipelined memory subsystem of claim 5 wherein said pipelined memory system stores computer instructions.
8 . The pipelined memory subsystem of claim 5 wherein said high-latency memory system comprises embedded DRAM.
9 . The First-In First-Out (FIFO) memory subsystem of claim 1 wherein said FIFO memory controller responds with data retrieved from said high-latency memory system after responding with data from said low-latency memory system.
10 . The First-In First-Out (FIFO) memory subsystem of claim 1 wherein said low-latency memory system stores at least enough data to last (L L -L H plus a logic processing time) seconds at said guaranteed minimum rate.
11 . The First-In First-Out (FIFO) memory subsystem of claim 1 wherein said FIFO memory controller replenishes said low-latency memory system with data retrieved from said high-latency memory system after responding to a request.
12 . The pipelined memory subsystem of claim 6 wherein said low-latency memory system buffers memory write requests in order to respond to a read request to a memory location having a pending write request.
13 . A method of handling requests in a First-In First-Out (FIFO) memory subsystem that provides FIFO memory services at a guaranteed minimum rate, said method comprising:
receiving a read request;
initiating a request to a high latency memory system, said high-latency memory system having a latency of L H seconds;
immediately respond to said read request with a low-latency memory system, said low-latency memory having a latency of L L , said low-latency memory system storing at least enough data to last L L -L H seconds at said guaranteed minimum rate; and
14 . The method of handling requests in a First-In First-Out (FIFO) memory subsystem as set forth in claim 13 wherein said high-latency memory system has a memory bandwidth sufficient to handle sustained FIFO requests at said guaranteed minimum rate.
15 . The method of handling requests in a First-In First-Out (FIFO) memory subsystem as set forth in claim 13 wherein said FIFO memory system stores network packets.
16 . The method of handling requests in a First-In First-Out (FIFO) memory subsystem as set forth in claim 13 wherein said high-latency memory system comprises embedded DRAM.
17 . The method of handling requests in a First-In First-Out (FIFO) memory subsystem as set forth in claim 13 wherein said FIFO memory controller responds with data retrieved from said high-latency memory system after responding with data from said low-latency memory system.
18 . The method of handling requests in a First-In First-Out (FIFO) memory subsystem as set forth in claim 13 wherein said low-latency memory system stores at least enough data to last (L L -L H plus a logic processing time) seconds at said guaranteed minimum rate.
19 . The method of handling requests in a First-In First-Out (FIFO) memory subsystem as set forth in claim 13 wherein said FIFO memory controller replenishes said low-latency memory system with data retrieved from said high-latency memory system after responding to a request.