Data processor having unified memory architecture using register to optimize memory access
View Patent ↗In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory 200 is generated from the CPU 310 , the memory controller 400 holds it once, requests the display controller 560 to stop the access to the memory 200 which is in execution, when data to the access executed already is transferred from the memory 200 , holds it, and transfers the access request from the CPU bus 310 which is held by the memory 200 . When the access from the CPU bus 310 ends, the memory controller 400 restarts the access stopped in the display controller 560 and passes the held data to the display controller 560.
1. A graphics display device comprising:
a CPU, the CPU generating drawing procedure information including graphic diagrams to be displayed and top (apex) parameters thereof;
a graphics memory, the graphics memory storing the drawing procedure information generated by the CPU and drawing data to be output to a display unit; and
a graphics processor which performs drawing access for the drawing procedure information, stores the drawing data in the graphics memory and further reads out the drawing data for outputting the same to the display unit, the graphics memory permitting access from both the CPU and the graphics processor,
wherein when the CPU writes the data in the graphics memory, the CPU causes to temporarily store an address and the data to be written in a FIFO within the graphics processor, and when under the condition that the data is stored in the FIFO and no new data are written from the CPU to the FIFO for a predetermined period, the graphics processor writes the data stored in the FIFO into the graphics memory according to the address,
wherein the graphics processor varies data storing timing in the graphics memory according to a cache system of a cache memory, said cache system being provided in the CPU and transferring data to the graphics memory, and
wherein the graphics processor further comprises:
a CPU interface;
a counter;
a match detector; and
a flip-flop,
wherein when the CPU performs a store operation to the graphics memory, a write request signal is sent from the CPU interface, the counter is incremented, and a write address and data of the CPU are stored in the FIFO,
wherein the match detector compares a value of the counter with a capacity of the FIFO, and
wherein the flip-flop is set if it is determined that the FIFO is full as a result of the comparison, such that the CPU interface is notified that the FIFO is busy and the CPU is prevented from storing any more data.
2. The graphic display device according to claim 1 , wherein the CPU interface receives drawing procedure information generated by the CPU including graphic diagrams to be displayed and top (apex) parameters thereof.
3. A graphics display device comprising:
a CPU, the CPU generating drawing procedure information including graphic diagrams to be displayed and top (apex) parameters thereof;
a graphics memory, the graphics memory storing the drawing procedure information generated by the CPU and drawing data to be output to a display unit; and
a graphics processor which performs drawing access for the drawing procedure information, stores the drawing data in the graphics memory and further reads out the drawing data for outputting the same to the display unit, the graphics memory permitting access from both the CPU and the graphics processor,
wherein when the CPU writes the data in the graphics memory, the CPU causes to temporarily store an address and the data to be written in a FIFO within the graphics processor, and when under the condition that the data is stored in the FIFO and no new data are written from the CPU to the FIFO for a predetermined period, the graphics processor writes the data stored in the FIFO into the graphics memory according to the address,
wherein the graphics processor varies data storing timing in the graphics memory according to a cache system of a cache memory, said cache system being provided in the CPU and transferring data to the graphics memory, and
wherein the graphics processor further comprises:
a memory interface circuit;
a read counter;
a write counter;
a match detector; and
a flip-flop,
wherein when a write request to the graphics memory is output to the memory interface circuit, and data is written, the memory interface circuit updates the read counter,
wherein the match detector compares a value of the read counter with a value of the write counter, and
wherein the flip-flop is reset if it is determined that the value of the read counter and the value of the write counter match.
4. The graphic display device according to claim 3 , wherein the memory interface circuit provides an interface for storing the drawing procedure information and drawing data in the graphics memory and reading out the drawing data from the graphics memory for outputting to the display unit.
5. A graphics display device comprising:
a CPU, the CPU generating drawing procedure information including graphic diagrams to be displayed and top (apex) parameters thereof;
a graphics memory, the graphics memory storing the drawing procedure information generated by the CPU and drawing data to be output to a display unit; and
a graphics processor which performs drawing access for the drawing procedure information, stores the drawing data in the graphics memory and further reads out the drawing data for outputting the same to the display unit, the graphics memory permitting access from both the CPU and the graphics processor,
wherein when the CPU writes the data in the graphics memory, the CPU causes to temporarily store an address and the data to be written in a FIFO within the graphics processor, and when the CPU performs reading from the graphics memory, the graphics processor writes the data stored in the FIFO into the graphics memory according to the address, before the CPU starts the reading,
wherein the graphics processor varies data storing timing in the graphics memory according to a cache system of a cache memory, said cache system being provided in the CPU and transferring data to the graphics memory, and
wherein the graphics processor further comprises:
a CPU interface;
a counter;
a match detector; and
a flip-flop,
wherein when the CPU performs a store operation to the graphics memory, a write request signal is sent from the CPU interface, the counter is incremented, and a write address and data of the CPU are stored in the FIFO,
wherein the match detector compares a value of the counter with a capacity of the FIFO, and
wherein the flip-flop is set if it is determined that the FIFO is full as a result of the comparison, such that the CPU interface is notified that the FIFO is busy and the CPU is prevented from storing any more data.
6. The graphic display device according to claim 5 , wherein the CPU interface receives drawing procedure information generated by the CPU including graphic diagrams to be displayed and top (apex) parameters thereof.
7. A graphics display device comprising:
a CPU, the CPU generating drawing procedure information including graphic diagrams to be displayed and top (apex) parameters thereof;
a graphics memory, the graphics memory storing the drawing procedure information generated by the CPU and drawing data to be output to a display unit; and
a graphics processor which performs drawing access for the drawing procedure information, stores the drawing data in the graphics memory and further reads out the drawing data for outputting the same to the display unit, the graphics memory permitting access from both the CPU and the graphics processor,
wherein when the CPU writes the data in the graphics memory, the CPU causes to temporarily store an address and the data to be written in a FIFO within the graphics processor, and when the CPU performs reading from the graphics memory, the graphics processor writes the data stored in the FIFO into the graphics memory according to the address, before the CPU starts the reading,
wherein the graphics processor varies data storing timing in the graphics memory according to a cache system of a cache memory, said cache system being provided in the CPU and transferring data to the graphics memory, and
wherein the graphics processor further comprises:
a memory interface circuit;
a read counter;
a write counter;
a match detector; and
a flip-flop,
wherein when a write request to the graphics memory is output to the memory interface circuit, and data is written, the memory interface circuit updates the read counter,
wherein the match detector compares a value of the read counter with a value of the write counter, and
wherein the flip-flop is reset if it is determined that the value of the read counter and the value of the write counter match.
8. The graphic display device according to claim 7 , wherein the memory interface circuit provides an interface for storing the drawing procedure information and drawing data in the graphics memory and reading out the drawing data from the graphics memory for outputting to the display unit.