Semiconductor device and method for fabricating the same
The semiconductor device of the present invention includes: a gate insulating film formed on a semiconductor region of a first conductivity type; a gate electrode formed on the gate insulating film; and a channel doped layer of the first conductivity type formed in the semiconductor region beneath the gate electrode. The channel doped layer contains carbon as an impurity.
1 . A semiconductor device comprising:
a gate insulating film formed on a semiconductor region of a first conductivity type;
a gate electrode formed on the gate insulating film; and
a channel doped layer of the first conductivity type, containing carbon as an impurity and formed in the semiconductor region beneath the gate electrode.
2 . The device of claim 1 , further comprising:
sidewalls formed on lateral faces of the gate electrode, and
source/drain doped layers of a second conductivity type formed in the semiconductor region alongside the respective sidewalls,
wherein the source/drain doped layers do not contain the carbon.
3 . The device of claim 2 , wherein the source/drain doped layers are formed spaced from the channel doped layer.
4 . The device of claim 1 , further comprising extended doped layers of a second conductivity type formed in the semiconductor region below the sides of the gate electrode.
5 . The device of claim 4 , further comprising pocket doped layers of the first conductivity type formed in the semiconductor region under and in contact with the extended doped layers.
6 . The device of claim 1 , wherein dopant ions introduced into the channel doped layer are heavy ions having a relatively high mass number.
7 . The device of claim 6 , wherein the heavy ions are indium ions.
8 . The device of claim 1 , wherein the semiconductor region is made of silicon.
9 . A semiconductor device comprising:
a gate insulating film formed on a semiconductor region of a first conductivity type;
a gate electrode formed on the gate insulating film;
extended doped layers of a second conductivity type formed in the semiconductor region below the sides of the gate electrode; and
pocket doped layers of the first conductivity type, containing carbon as an impurity and formed in the semiconductor region under and in contact with the extended doped layers.
10 . The device of claim 9 , further comprising:
sidewalls formed on lateral faces of the gate electrode, and
source/drain doped layers of the second conductivity type formed in the semiconductor region alongside the respective sidewalls,
wherein in the source/drain doped layers, regions away from the pocket doped layers do not contain the carbon.
11 . The device of claim 9 , wherein dopant ions introduced into the pocket doped layers are heavy ions having a relatively high mass number.
12 . The device of claim 11 , wherein the heavy ions are indium ions.
13 . The device of claim 9 , wherein the semiconductor region is made of silicon.
14 . A method for fabricating a semiconductor device, comprising the steps of:
(a) implanting first dopant ions of a first conductivity type into a semiconductor region of the first conductivity type, thereby forming a channel implantation layer;
(b) selectively implanting second dopant ions, which are made of carbon or made of molecules containing carbon, into a channel formation region in the semiconductor region, thereby forming a carbon implantation layer in the channel implantation layer;
(c) subjecting, after the steps (a) and (b), the semiconductor region to a first heat treatment so as to cause diffusion of the first dopant ions from the channel implantation layer and the carbon implantation layer, thereby forming a channel doped layer in the semiconductor region;
(d) forming a gate insulating film on the channel doped layer in the semiconductor region; and
(e) forming a gate electrode on the gate insulating film,
wherein the channel doped layer contains the carbon of the second dopant ions.
15 . The method of claim 14 , further comprising, between the steps (a) and (b), the step of forming, on the semiconductor region, a mask pattern having an opening that exposes the channel formation region,
wherein in the step (b), the second dopant ions are selectively implanted into the channel formation region by using the mask pattern, thereby forming the carbon implantation layer.
16 . The method of claim 14 , further comprising, before the step (a), the step of forming, on the semiconductor region, a mask pattern having an opening that exposes the channel formation region,
wherein in the step (a), the first dopant ions are selectively implanted into the channel formation region by using the mask pattern, thereby forming the channel implantation layer, and
in the step (b), the second dopant ions are selectively implanted into the channel formation region by using the mask pattern, thereby forming the carbon implantation layer.
17 . The method of claim 14 , further comprising, after the step (e), the step (f) of forming extended implantation layers by implanting third dopant ions of a second conductivity type into the semiconductor region with the gate electrode used as a mask; and
after the step (f), the step (g) of subjecting the semiconductor region to a second heat treatment, thereby forming extended doped layers by diffusion of the third dopant ions from the extended implantation layers.
18 . The method of claim 17 , further comprising, between the steps (e) and (g), the step of implanting fourth dopant ions of the first conductivity type into the semiconductor region with the gate electrode used as a mask, thereby forming pocket implantation layers,
wherein in the step (g), the second heat treatment causes diffusion of the fourth dopant ions from the pocket implantation layers, thereby forming pocket doped layers under the extended doped layers.
19 . The method of claim 14 , further comprising, after the step (e), the step (h) of forming sidewalls on lateral faces of the gate electrode;
after the step (h), the step (i) of implanting fifth dopant ions of a second conductivity type into the semiconductor region with the sidewalls used as a mask, thereby forming source/drain implantation layers; and
after the step (i), the step (j) of subjecting the semiconductor region to a third heat treatment to cause diffusion of the fifth dopant ions from the source/drain implantation layers, thereby forming source/drain doped layers.
20 . The method of claim 14 , further comprising, before the step (a), the steps of:
(1) forming a dummy gate electrode on the semiconductor region;
(2) forming sidewalls on both lateral faces of the dummy gate electrode;
(3) forming, after the step (2), on the semiconductor region, an insulating film from which the upper surface of the dummy gate electrode is exposed; and
(4) selectively removing the dummy gate electrode after the step (3), thereby exposing a part of the semiconductor region between the sidewalls,
wherein in the step (a), the first dopant ions are implanted into the exposed part of the semiconductor region with the insulating film used as a mask, thereby forming the channel implantation layer; and
in the step (b), the second dopant ions are implanted into the exposed part of the semiconductor region with the insulating film used as a mask, thereby forming the carbon implantation layer.
21 . The method of claim 14 , wherein the first dopant ions are heavy ions having a relatively high mass number.
22 . The method of claim 21 , wherein in the step (a), the channel implantation layer does not become amorphous due to the implantation of the first dopant ions.
23 . The method of claim 21 , wherein the heavy ions are indium ions.
24 . The method of claim 14 , wherein the semiconductor region is made of silicon.
25 . A method for fabricating a semiconductor device, comprising the steps of:
(a) forming a gate insulating film on a semiconductor region of a first conductivity type;
(b) forming a gate electrode on the gate insulating film;
(c) implanting first dopant ions of a second conductivity type into the semiconductor region with the gate electrode used as a mask, thereby forming extended implantation layers;
(d) implanting second dopant ions of the first conductivity type into the semiconductor region with the gate electrode used as a mask, thereby forming pocket implantation layers;
(e) selectively implanting third dopant ions, which are made of carbon or made of molecules containing carbon, into pocket formation regions in the semiconductor region, thereby forming carbon implantation layers; and
(f) subjecting the semiconductor region to a first heat treatment after the steps (c), (d), and (e) have been performed, whereby diffusion of the first dopant ions from the extended implantation layers is caused to form extended doped layers in the semiconductor region below the sides of the gate electrode, and diffusion of the second dopant ions from the pocket implantation layers is caused to form pocket doped layers under the extended doped layers,
wherein the pocket doped layers contain the carbon of the third dopant ions.
26 . The method of claim 25 , further comprising, after the step (f), the step (g) of forming sidewalls on lateral faces of the gate electrode;
after the step (g), the step (h) of implanting fourth dopant ions of the second conductivity type into the semiconductor region with the sidewalls used as a mask, thereby forming source/drain implantation layers; and
after the step (h), the step (i) of subjecting the semiconductor region to a second heat treatment to cause diffusion of the fourth dopant ions from the source/drain implantation layers, thereby forming source/drain doped layers.
27 . The method of claim 25 , wherein the second dopant ions are heavy ions having a relatively high mass number.
28 . The method of claim 27 , wherein the heavy ions are indium ions.
29 . The method of claim 25 , wherein the semiconductor region is made of silicon.