Efficient hardware allocation of processes to processors
A dispatcher module has a queue to store task requests. The dispatcher also has a task arbiter to select a current task for assignment from the task requests and a unit arbiter to identify and assign the task to an available processing unit, such that the current task is not assigned to a previously-assigned processing unit.
1 . A dispatcher module, comprising:
a queue to store task requests;
a task arbiter to select a current task for assignment from the task requests;
a unit arbiter to identify and assign the task to an available processing unit, such that the current task is not assigned to a previously-assigned processing unit.
2 . The dispatcher module of claim 1 , the queue to store task requests further comprising a memory.
3 . The dispatcher module of claim 1 , a queue further comprising a subqueue for processing unit to processing unit tasks, a subqueue for central processing unit to processing unit tasks, and a subqueue for parser to processing unit tasks.
4 . The dispatcher module of claim 1 , the queue having a read pointer and a write pointer.
5 . The dispatcher module of claim 1 , the queue further comprising a comparator to compare the read pointer and the write pointer.
6 . The dispatcher module of claim 5 , the comparator further to assert a task arbiter enable signal if the read pointer and write pointer do not match.
7 . The dispatcher of claim 1 , the unit arbiter further to receive state signals from each of a group of processing units.
8 . The dispatcher of claim 1 , the dispatcher further comprising a memory to store an identifier for a previously used processing unit.
9 . The dispatcher of claim 1 , the dispatcher to produce a valid response signal, a processing unit identifier for a selected processing unit, and a program counter signal.
10 . The dispatcher of claim 1 , the task arbiter and the unit arbiter to employ a round-robin arbiter sequence.
11 . A system comprising:
an ingress buffer to accept incoming data packets having headers;
a parser to parse the headers and determine tasks to be accomplished based upon the headers;
an array of processing units;
a central processing unit;
a dispatcher to:
monitor status of each processing unit in the array of processing units;
receive a task request from one of the parser, the central processing unit and the array of processing units;
assign tasks selected from the task requests to processing units based upon the status, such that the tasks selected are not assigned to a previously assigned processing unit.
12 . The system of claim 11 , each processing unit in the array of processing units having a state machine coupled to the dispatcher, such that the state machine provides input regarding the status of the processing unit.
13 . The system of claim 11 , the dispatcher further comprising a task arbiter to select tasks from the task requests.
14 . The system of claim 11 , the dispatcher further comprising a unit arbiter to assign processing units based upon the status of each processing unit.
15 . The system of claim 11 , the dispatcher further comprising a queue to store task requests.
16 . The system of claim 11 , the dispatcher to assign tasks further to produce a signal indicating an offset into the ingress buffer and a program counter to the processing unit assigned a task when the task is from the parser.
17 . The system of claim 11 , the dispatcher to assign tasks further to produce a program counter, an initial SEP address, and arguments, when the task is from the central processing unit.
18 . The system of claim 11 , the dispatcher to assign tasks further to produce a program counter and arguments, when the task is from another processing unit.
19 . A method of distributing tasks, comprising:
determining if there is a task request waiting;
determining if there is at least one processing unit available;
assigning a task associated with the request to an available processing unit, such that the task is not assigned to a previously assigned processing unit, if there are more than two processing units available;
advancing a write pointer for the available processing unit; and
storing an identifier for the available processing unit as the previously assigned processing unit.
20 . The method of claim 19 , determining if there is a task request waiting further comprises comparing a write pointer and a read pointer for a queue to determine if the write pointer and the read pointer are not the same.
21 . The method of claim 19 , determining if there is at least one processing unit available further comprising monitoring inputs from an array of processing units.
22 . The method of claim 19 , further comprising assigning the available processing unit if there is only one available processing unit without regard to the previously assigned processor.
23 . The method of claim 19 , assigning a task to an available processing unit further comprising assigning the task to an available processing unit with the highest priority.
24 . The method of claim 19 , further comprising rearranging priorities for available processing units after assignment of a task, based upon which processing unit was assigned the task.