Packet output buffer for semantic processor
An embodiment of the invention is a processor comprising a direct execution parser configured to control the processing of digital data by semantically parsing data; a plurality of semantic processing units configured to perform data operations when prompted by the direct execution parser; and a plurality of output buffers for buffering data received from the plurality of semantic processing units. Another embodiment of the invention is an interface circuit comprising a packer circuit for receiving data from a semantic processing unit and a plurality of buffers for receiving the data. The interface circuit unloads the data received to an interface.
1 . An interface circuit, comprising:
a packer circuit for receiving data from a semantic processing unit; and
a plurality of buffers for buffering the data received from the semantic processing unit.
2 . The interface circuit of claim 1 , wherein the packer circuit comprises:
an address decoder for determining a number of valid bytes in the data received from the semantic processing unit.
3 . The interface circuit of claim 2 , wherein the address decoder determines the number of valid bytes in the data according to a value encoded in the address of the data received.
4 . The interface circuit of claim 2 , wherein the packer circuit further comprises:
a holding register for storing the data if the number of bytes in the data received from the semantic processing unit is less than a predetermined number.
5 . The interface circuit of claim 1 , further comprising:
a controller for controlling access to the plurality of buffers by the semantic processing unit.
6 . The interface circuit of claim 1 , further comprising:
an egress state machine for unloading the data in the plurality of buffers to an interface.
7 . The interface circuit of claim 6 , wherein the interface is a network interface port.
8 . The interface circuit of claim 6 , wherein the interface is a peripheral component interface.
9 . The interface circuit of claim 6 , wherein the egress state machine unloads the data in the plurality of buffers to the interface in a round-robin manner.
10 . The interface circuit of claim 1 , further comprising an error detection circuit configured to notify the semantic processing unit of errors in the buffered data.
11 . The interface circuit of claim 1 , wherein the error detection circuit computes Cyclic Redundancy Codes using the buffered data.
12 . The interface circuit of claim 11 , wherein the error detection circuit sends error information to the semantic processing unit.
13 . The interface circuit of claim 11 , wherein the error detection circuit prevents access by the semantic processing unit when errors are detected.
14 . A processor, comprising:
a direct execution parser configured to control the processing of digital data by semantically parsing data;
a plurality of semantic processing units configured to perform data operations when prompted by the direct execution parser; and
a plurality of output buffers for buffering data received from the plurality of semantic processing units.
15 . The processor of claim 14 , wherein each of the plurality of output buffers is configured for access by only one of the plurality of semantic processing units at any given time.
16 . The processor of claim 14 , further comprising a token mechanism for indicating which semantic processing unit can access the plurality of output buffers.
17 . The processor of claim 14 , wherein the plurality of output buffers send data received from the plurality of semantic processing units to a network interface port.
18 . The processor of claim 14 , wherein the plurality of output buffers send data received from the plurality of semantic processing unit to a peripheral component.