Bit labeling for amplitude phase shift constellation used with low density parity check (LDPC) codes
An approach is provided for bit labeling of a signal constellation. A transmitter generates encoded signals using, according to one embodiment, a structured parity check matrix of a Low Density Parity Check (LDPC) code. The transmitter includes an encoder for transforming an input message into a codeword represented by a plurality of set of bits. The transmitter includes logic for mapping non-sequentially (e.g., interleaving) one set of bits into a higher order constellation (Quadrature Phase Shift Keying (QPSK), 8-PSK, 16-APSK (Amplitude Phase Shift Keying), 32-APSK, etc.), wherein a symbol of the higher order constellation corresponding to the one set of bits is output based on the mapping.
1. A method for supporting bit labeling, the method comprising:
receiving, at a receiver, a set of encoded bits of a binary Low Density Parity Check (LDPC) codeword, wherein the codeword has a parity check matrix with a structure that provides contiguous storage of edge values for decoding of the LDPC code;
storing the set of encoded bits on a column by column basis; and
outputting the encoded bits on a row by row basis for mapping to a signal constellation.
2. A method according to claim 1 , wherein the signal constellation is 8-PSK (Phase Shift Keying) and has adjacent clockwise symbols representing bits, respectively, in the following sequence, 000, 001, 101, 111, 011, 010, 110, and 100.
3. A method according to claim 1 , wherein the signal constellation corresponds to 16-APSK (Amplitude Phase Shift Keying);
wherein a first set of adjacent clockwise symbols representing bits, respectively, in the following sequence, 1100, 1101, and 1111, 1110; and
wherein a second set of adjacent clockwise symbols representing bits, respectively, in the following sequence, 0000, 0100, 0101, 0001, 1001, 1011, 0011, 0111, 0110, 0010, 1010, and 1000.
4. A method according to claim 1 , wherein the signal constellation corresponds to 32-APSK (Amplitude Phase Shift Keying);
wherein a first set of adjacent clockwise symbols representing bits, respectively, in the following sequence, 10001, 10011, 10111, and 10101;
wherein a second set of adjacent clockwise symbols representing bits, respectively, in the following sequence, 00000, 10000, 10010, 00010, 00011, 00111, 00110, 10110, 10100, 00100, 00101, and 00001;
wherein a third set of adjacent clockwise symbols representing bits, respectively, in the following sequence, 11001, 01000, 11000, 11010, 01010, 11011, 01011, 01111, 11111, 01110, 11110, 11100, 01100, 11101, 01101, and 01001.
5. A method according to claim 1 , wherein the signal constellation represents a Quadrature Phase Shift Keying (QPSK) modulation scheme, the method further comprising:
determining an i th QPSK symbol based on the set of 2i th and (2i+1) th LDPC encoded bits,
wherein i=0, 1, 2 . . . , N/2−1, and N is the coded LDPC block size.
6. A method according to claim 1 , wherein the signal constellation represents an 8-PSK modulation scheme, the method further comprising:
determining an i th 8-PSK symbol based on the set of (N/3+i) th , (2N/3+i) th and i th LDPC encoded bits, wherein i=0, 1, 2, . . . , N/3−1, and N is the coded LDPC block size.
7. A method according to claim 1 , wherein the signal constellation represents a 16-APSK (Amplitude Phase Shift Keying) modulation scheme, the method further comprising:
determining an i th 16-APSK symbol based on the set of (N/2+2i) th , 2i th , (N/2+2i+1) th and (2i+1) th LDPC encoded bits, wherein i=0, 1, 2, . . . , N/3−1, and N is the coded LDPC block size.
8. A method according to claim 1 , wherein the signal constellation represents a 32-APSK (Amplitude Phase Shift Keying) modulation scheme, the method further comprising:
determining an i th 32-APSK symbol based on the set of (N/5+i) th , (2N/5+i) th , (4N/5+i) th , (3N/5+i) th and i th LDPC encoded bits, wherein i=0, 1, 2, . . . , N/5−1, and N is the coded LDPC block size.
9. A receiver configured to receive a signal representing the encoded bits in accordance with claim 1 .
10. A mapper for supporting bit labeling, the mapper comprising:
means for receiving a set of encoded bits of a binary Low Density Parity Check (LDPC) codeword, wherein the codeword has a parity check matrix with structure that provides contiguous storage of edge values for decoding of the LDPC code;
means for storing the set of encoded bits on a column by column basis; and
means for outputting the encoded bits on a row by row basis for a non-sequential read operation, wherein the output encoded bits are mapped to a signal constellation.
11. A mapper according to claim 10 , wherein the signal constellation is 8-PSK (Phase Shift Keying) and has adjacent clockwise symbols of the following sequence, 000, 001, 101, 111, 011,010, 110, and 100.
12. A mapper according to claim 10 , wherein the signal constellation corresponds to 16-APSK (Amplitude Phase Shift Keying);
wherein a first set of adjacent clockwise symbols representing bits, respectively, in the following sequence, 1100, 1101, and 1111, 1110; and
wherein a second set of adjacent clockwise symbols representing bits, respectively, in the following sequence, 0000, 0100, 0101, 0001, 1001, 1011, 0011, 0111, 0110, 0010, 1010, and 1000.
13. A mapper according to claim 10 , wherein the signal constellation corresponds to 32-APSK (Amplitude Phase Shift Keying);
wherein a first set of adjacent clockwise symbols representing bits, respectively, in the following sequence, 10001, 10011, 10111, and 10101;
wherein a second set of adjacent clockwise symbols representing bits, respectively, in the following sequence, 00000, 10000, 10010, 00010, 00011, 00111, 00110, 10110, 10100, 00100, 00101, and 00001;
wherein a third set of adjacent clockwise symbols representing bits, respectively, in the following sequence, 11001, 01000, 11000, 11010, 01010, 11011, 01011, 01111, 11111, 01110, 11110, 11100, 01100, 11101, 01101, and 01001.
14. A mapper according to claim 10 , wherein the signal constellation represents a Quadrature Phase Shift Keying (QPSK) modulation scheme, the mapper further comprising:
determining an i th QPSK symbol based on the set of 2i th and (2i+1) th LDPC encoded bits, wherein i=0, 1, 2 . . . , N/2−1, and N is the coded LDPC block size.
15. A mapper according to claim 10 , wherein the signal constellation represents an 8-PSK modulation scheme, the mapper further comprising:
determining an i th 8-PSK symbol based on the set of (N/3+i) th , (2N/3+i) th and i th LDPC encoded bits, wherein i=0, 1, 2, . . . , N/3−1, and N is the coded LDPC block size.
16. A mapper according to claim 10 , wherein the signal constellation represents a 16-APSK (Amplitude Phase Shift Keying) modulation scheme, the mapper further comprising:
determining an i th 16-APSK symbol based on the set of (N/2+2i) th , 2i th , (N/2+2i+1) th and (2i+1) th LDPC encoded bits, wherein i=0, 1, 2, . . . , N/3−1, and N is the coded LDPC block size.
17. A mapper according to claim 10 , wherein the higher order constellation represents a 32-APSK (Amplitude Phase Shift Keying) modulation scheme, the mapper further comprising:
determining an i th 32-APSK symbol based on the set of (N/5+i) th , (2N/5+i) th , (4N/5+i) th , (3N/5+i) th and i th LDPC encoded bits, wherein i=0, 1, 2, . . . , N/5−1, and N is the coded LDPC block size.
18. An apparatus comprising:
means for receiving one of a plurality of set of bits of a codeword from a binary Low Density Parity Check (LDPC) encoder for transforming an input message into the codeword, wherein the codeword has a parity check matrix with a structure that provides contiguous storage of edge values for decoding of the LDPC code;
means for writing N encoded bits to a block interleaver on a column by column basis, N being an integer;
means for reading out the encoded bits on a row by row basis;
means for mapping the read out encoded bits into a higher order constellation; and
means for outputting a symbol of the higher order constellation corresponding to the one set of bits based on the mapping for transmission over an Additive White Gaussian Noise (AWGN) channel.
19. An apparatus according to claim 18 ,
wherein the block interleaver has N/3 rows and 3 columns when the higher order modulation is 8-PSK (Phase Shift Keying), N/4 rows and 4 columns when the higher order modulation is 16-APSK (Amplitude Phase Shift Keying), and N/5 rows and 5 columns when the higher order modulation is 32-APSK.
20. An apparatus comprising:
means for demodulating a received Low Density Parity Check (LDPC) encoded signal, over an Additive White Gaussian Noise (AWGN) channel, representing a codeword having a parity check matrix with a structure that provides contiguous storage of edge values for decoding of the LDPC code, wherein the encoded signal being modulated according to a non-sequential mapping, based on the structure of the codeword, of a plurality of bits corresponding to the codeword, wherein the N encoded bits are written to a block interleaver column by column and read out row by row; and
means for decoding the codeword associated with the encoded signal.
21. An apparatus according to claim 20 , wherein the block interleaver has N/3 rows and 3 columns when the modulation is 8-PSK (Phase Shift Keying), N/4 rows and 4 columns when the modulation is 16-APSK (Amplitude Phase Shift Keying), and N/5 rows and 5 columns when the modulation is 32-APSK.
22. A method comprising:
decoding a Low Density Parity Check (LDPC) encoded signal, wherein the signal was modulated according to a non-sequential mapping of a plurality of bits, corresponding to a codeword represented by the signal, to a signal constellation by writing the encoded bits to a block interleaver column by column and read out row by row, the codeword having a parity check matrix with a structure that provides contiguous storage of edge values for decoding of the LDPC code.
23. A method according to claim 22 , wherein the block interleaver has N/3 rows and 3 columns when the modulation is 8-PSK (Phase Shift Keying), N/4 rows and 4 columns when the modulation is 16-APSK (Amplitude Phase Shift Keying), and N/5 rows and 5 columns when the modulation is 32-APSK.
24. A decoder comprising:
logic configured to decode a Low Density Parity Check (LDPC) encoded signal, wherein the signal was modulated according to a non-sequential mapping of a plurality of bits, corresponding to a codeword represented by the signal, to a signal constellation by writing the encoded bits to a block interleaver column by column and read out row by row, the codeword having a parity check matrix with a structure that provides contiguous storage of edge values for decoding of the LDPC code.
25. A decoder according to claim 24 , wherein the block interleaver has N/3 rows and 3 columns when the modulation is 8-PSK (Phase Shift Keying), N/4 rows and 4 columns when the modulation is 16-APSK (Amplitude Phase Shift Keying), and N/5 rows and 5 columns when the modulation is 32-APSK.