System for reducing the latency of exclusive read requests in a symmetric multi-processing system

1. A symmetric multi-processing system for processing exclusive read requests, the system including a plurality of cell boards, each including at least one CPU and cache memory, connected to at least one crossbar switch, the system comprising:

the cache memory on each one of the cell boards being write-through cache memory;

a modified line list, on each said crossbar switch, including storage for cache lines that have been modified in the cache memory of each of the cell boards;

a cache coherency directory, on each said crossbar switch, for recording the address, the status, and the location of each of the cache lines in the system; and

wherein the modified line list is accessed, to obtain a copy of a requested cache line for each of the exclusive read requests from the cell boards not containing the requested cache line.

2. The system of claim 1 , wherein the status is a state selected from the group consisting of invalid, shared, and exclusive states.

3. The system of claim 1 , wherein, when at least one said crossbar switch has a copy of the requested cache line, a copy of the requested cache line is sent, from the crossbar switch having a copy of the requested cache line, to the cell board requesting the requested cache line, and the cache coherency directory is updated to indicate a change in ownership of the requested cache line.

4. The system of claim 1 , wherein, when no said crossbar switch has a copy of the requested cache line, but a copy of the requested cache line exists on a non-home cell board, a copy of the requested cache line is stored on one said crossbar switch, and the cache coherency directory is updated to indicate exclusive ownership by the cell board requesting the requested cache line.

5. The system of claim 1 , wherein, when no copy of the requested cache line exists on any said crossbar switch, and the only said copy is stored on a home cell board, the requested cache line is forwarded to the cell board requesting the requested cache line, the copy is stored on one said crossbar switch, and the cache coherency directory is updated to indicate exclusive ownership by the cell board requesting the requested cache line.

6. The system of claim 1 , wherein, when no said crossbar switch has a copy of the requested cache line, but a copy of the requested cache line exists on one of the non-home cell boards, the requested cache line is sent, from the crossbar switch having a copy of the requested cache line, to the cell board requesting the requested cache line, a copy of the requested cache line is stored on one said crossbar switch, and the cache coherency directory is updated to indicate exclusive ownership by the cell board requesting the requested cache line.

7. The system of claim 1 , wherein, when remote shared copies of the requested cache line are present in the system, the requested cache line is fetched from its home cell and sent to the cell board requesting the requested cache line, a copy of the requested cache line is stored on one said crossbar switch, and the cache coherency directory is updated to indicate exclusive ownership by the cell board requesting the requested cache line.

8. A symmetric multi-processing system for processing exclusive read requests, the system including a plurality of cell boards, each including at least one CPU and cache memory, connected to a crossbar switch, the system comprising:

write-through cache memory on a plurality of the cell boards;

a modified line list, on the crossbar switch, including storage for cache lines that have been modified in the cache memory of each of the cell boards; and

a cache coherency directory, on said crossbar switch, for recording the address, the status, and the location of each of the cache lines in the system;

wherein the modified line list is accessed, to obtain a copy of a requested cache line for each of the exclusive read requests from the cell boards not containing the requested cache line; and

wherein, when the crossbar switch has a copy of the requested cache line, a copy of the requested cache line is sent to the cell board requesting the requested cache line and the cache coherency directory is updated to indicate a change in ownership of the requested cache line.

9. The system of claim 8 , wherein, when no said crossbar switch has a copy of the requested cache line, but a copy of the requested cache line exists on a non-home cell board, a copy of the requested cache line is stored on one said crossbar switch, and the cache coherency directory is updated to indicate exclusive ownership by the cell board requesting the requested cache line.

10. A method for processing exclusive read requests in a symmetric multi-processing system including a plurality of cell boards, each including at least one CPU and cache memory, connected to at least one crossbar switch, the method comprising:

including write-through cache memory on each one of the cell boards;

including a modified line list, on each said crossbar switch, the modified line list including storage for cache lines that have been modified in the cache memory of each of the cell boards;

including a cache coherency directory on each said crossbar switch for recording the address, the status, and the location of each of the cache lines in the system; and

accessing the modified line list to obtain a copy of a requested cache line for each of the exclusive read requests from the cell boards not containing the requested cache line.

11. The method of claim 10 , wherein no copy of the requested cache line exists on any said crossbar switch, and the only copy of the requested cache line is stored on a home cell board, including the additional steps of:

forwarding the cache line to the requesting cell;

caching a copy of the requested cache line on one said crossbar switch; and

updating the cache coherency directory to indicate exclusive ownership by the cell board requesting the requested cache line.

12. The method of claim 10 , wherein at least one said crossbar switch has a copy of the requested cache line, including the additional steps of:

sending a copy of the requested cache line, from the crossbar switch having a copy of the requested cache line, to the cell board requesting the requested cache line; and

updating the cache coherency directory to indicate a change in ownership of the requested cache line.

13. The method of claim 10 , wherein no said crossbar switch has a copy of the requested cache line, but a copy of the requested cache line exists on one of the non-home cell boards, including the additional steps of:

sending the requested cache line to the cell board requesting the requested cache line;

storing a copy of the requested cache line on one said crossbar switch; and

updating the cache coherency directory to indicate exclusive ownership by the cell board requesting the requested cache line.

14. The system of claim 10 , wherein remote shared copies of the requested cache line are present in the system, including the additional steps of:

invalidating all copies of the requested cache line;

fetching the requested cache line from its home cell and sending the requested cache line to the cell board requesting the requested cache line;

storing a copy of the requested cache line on one said crossbar switch; and

updating the cache coherency directory to indicate exclusive ownership by the cell board requesting the requested cache line.

15. A method for processing exclusive read requests in a symmetric multi-processing system including a plurality of cell boards, each including at least one CPU and cache memory, connected to at least one crossbar switch, the method comprising:

including write-through cache memory on each one of the cell boards;

including a modified line list, on each said crossbar switch, the modified line list including storage for cache lines that have been modified in the cache memory of each of the cell boards;

including a cache coherency directory on each said crossbar switch for recording the address, the status, and the location of each of the cache lines in the system;

accessing the modified line list to obtain a copy of a requested cache line for each of the exclusive read requests from the cell boards not containing the requested cache line;

sending a copy of the requested cache line, from the crossbar switch having a copy of the requested cache line, to the cell board requesting the requested cache line; and

updating the cache coherency directory to indicate a change in ownership of the requested cache line.

16. The method of claim 15 , wherein, when no said crossbar switch has a copy of the requested cache line, but a copy of the requested cache line exists on a non-home cell board, a copy of the requested cache line is stored on one said crossbar switch, and the cache coherency directory is updated to indicate exclusive ownership by the cell board requesting the requested cache line.

17. A symmetric multi-processing system for processing exclusive read requests, the system including a plurality of cell boards having write-through cache memory, each of the cell boards including at least one CPU and cache memory, and each of the cell boards connected to at least one crossbar switch, the method comprising:

means for storing, on each said crossbar switch, cache lines that have been modified in the cache memory of each of the cell boards having write-through cache memory; and

means, on each said crossbar switch, for recording the address, the status, and the location of each of the cache lines in the system;

wherein the modified line list is accessed to obtain a copy of a requested cache line for each of the exclusive read requests from the cell boards not containing the requested cache line.

18. The system of claim 17 , wherein, when at least one said crossbar switch has a copy of the requested cache line, a copy of the requested cache line is sent, from the crossbar switch having a copy of the requested cache line, to the cell board requesting the requested cache line, and the cache coherency directory is updated to indicate a change in ownership of the requested cache line.

19. The system of claim 17 , wherein, when no said crossbar switch has a copy of the requested cache line, but a copy of the requested cache line exists on a non-home cell board, a copy of the requested cache line is stored on one said crossbar switch, and the cache coherency directory is updated to indicate exclusive ownership by the cell board requesting the requested cache line.