IP Library Granted Patent US 7,215,151
Granted Patent B2
US 7,215,151 · App. 11/186,753 · Granted May 8, 2007

Multi-stage light emitting diode driver circuit

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Quick Facts
Patent No.
US 7,215,151
App. No.
11/186,753
Granted
May 8, 2007
Kind
B2
Abstract

A multi-stage light emitting diode (LED) driver circuit is provided. The circuit includes a driver transistor coupled to an LED. The LED is coupled at a drain of the driver transistor and the driver transistor drives current to the LED. A first transistor stack is coupled between a gate of the driver transistor and ground. A first inverter stage is coupled to a common gate of the first transistor stack. The first inverter stage is further coupled between a high voltage source and ground. A second inverter stage is coupled to a common gate of the first inverter stage. The second inverter stage is further coupled between the high voltage source and ground. The circuit further includes a first transistor coupled between the high voltage source and gate of the driver transistor. The gate of the transistor is coupled to the first inverter stage.

Claims (54)

1. A multi-stage light emitting diode (LED) driver circuit, comprising:

a driver transistor coupled to an LED, wherein the LED is coupled at a drain of the driver transistor and the driver transistor drives current to the LED;

a first transistor stack coupled between a gate of the driver transistor and ground;

a first inverter stage coupled to a common gate of the first transistor stack, wherein the first inverter stage is coupled between a high voltage source and ground;

a second inverter stage coupled to a common gate of the first inverter stage, wherein the second inverter stage is coupled between the high voltage source and ground; and

a first transistor coupled between the high voltage source and the gate of the driver transistor, wherein the gate of the first transistor is coupled to the first inverter stage.

2. The circuit of claim 1 , wherein the first transistor stack comprises:

a pair of NMOS transistors connected in series, and wherein a drain of a first NMOS transistor in the pair is coupled to the gate of the driver transistor and a source of a second NMOS transistor in the pair is coupled to ground.

3. The circuit of claim 1 , wherein the driver transistor and the first transistor are PMOS transistors.

4. The circuit of claim 1 , wherein the first inverter stage comprises:

a first pair of PMOS transistors connected in series; and

an NMOS transistor, and wherein the first pair of PMOS transistors are coupled between the high voltage source and the NMOS transistor, the NMOS transistor is coupled to ground at a source of the NMOS transistor, and gates of the first pair of PMOS transistors and the NMOS transistor are commonly coupled to the second inverter stage.

5. The circuit of claim 4 , wherein the second inverter stage comprises:

a second pair of PMOS transistors connected in series;

a first NMOS transistor stack, wherein the first NMOS transistor stack comprises a pair of NMOS transistors connected in series; and

a resistor, wherein the second pair of PMOS transistors are coupled between the high voltage source and the resistor, the first NMOS transistor stack is coupled between the resistor and ground, the drain of one PMOS transistor in the second pair of PMOS transistors is coupled to the commonly coupled gates of the first inverter stage, and gates of the second pair of PMOS transistors and the first NMOS transistor stack are commonly coupled to an inverter.

6. A light emitting diode (LED) driver circuit, comprising:

a first inverter stage to output a first voltage;

a second inverter stage to output a second voltage;

a first transistor stack including a first pair of NMOS transistors connected in series;

a PMOS transistor coupled at a drain of the PMOS transistor to one NMOS transistor of the first transistor stack, wherein gates of the first pair of NMOS transistors of the first transistor stack and gates of PMOS transistor are commonly coupled to receive the first output voltage from the first inverter stage;

a driver transistor coupled at a gate of the driver transistor to the drain of the PMOS transistor and a drain of the one NMOS transistor of the first transistor stack; and

an LED coupled between a drain of the driver transistor and ground, wherein if the LED is off, a gate voltage of the driver transistor is high, the first output voltage is low and the second output voltage is high.

7. The circuit of claim 6 , wherein if the LED is on, the gate voltage of the driver transistor is low, the first output voltage is high and the second output voltage is low.

8. The circuit of claim 6 , wherein the driver transistor is a PMOS transistor.

9. The circuit of claim 6 , wherein the first inverter stage comprises:

a first pair of PMOS transistors connected in series; and

an NMOS transistor, and wherein the first pair of PMOS transistors are coupled between a high voltage source and the NMOS transistor, the NMOS transistor is coupled to ground at a source of the NMOS transistor, and gates of the first pair of PMOS transistors and the gate of NMOS transistor are commonly coupled to the second inverter stage.

10. The circuit of claim 6 , wherein the second inverter stage comprises:

a second pair of PMOS transistors connected in series;

a second transistor stack, and wherein the second stack comprises second pair of NMOS transistors connected in series; and

a resistor, and wherein the second pair of PMOS transistors are coupled between the high voltage source and the resistor, the second NMOS transistor stack is coupled between the resistor and ground, and the drain of one PMOS transistor in the second PMOS pair is coupled to the commonly coupled gates of the first inverter stage.

11. The circuit of claim 10 , further comprising:

an inverter, wherein gates of the second pair of PMOS transistors and gates of the second NMOS transistor stack are commonly coupled to the inverter.

12. A light emitting diode driver circuit, comprising:

a light emitting diode (LED);

a PMOS driver transistor coupled to the LED, wherein the LED is coupled at a drain of the PMOS driver transistor and the driver transistor drives current to the LED;

a first transistor stack coupled between a gate of the driver transistor and ground, wherein the first transistor stack including a pair of NMOS transistors connected in series; and

a first PMOS transistor coupled between a high voltage source and the gate of the PMOS driver transistor, wherein the gate of the PMOS driver transistor is at the high voltage source and the first transistor stack distributes voltage stress across the pair of NMOS transistors if the PMOS driver transistor is not driving current to the LED.

13. The circuit of claim 12 , wherein the gate of the PMOS driver transistor is at a ground voltage if the driver transistor is driving current to the LED and the LED is on.

14. The circuit of claim 12 , further comprising:

a first inverter stage coupled to a common gate of the first transistor stack, wherein the first inverter stage is coupled between the high voltage source and ground.

15. The circuit of claim 14 , wherein the first inverter stage comprises:

a first pair of PMOS transistors connected in series; and

an NMOS transistor, and wherein the pair of PMOS transistors are coupled between the high voltage source and the NMOS transistor, the NMOS transistor is coupled to ground at a source of the NMOS transistor, and gates of the first pair of PMOS transistors and gates of the NMOS transistor are commonly coupled to a second inverter stage.

16. The circuit of claim 14 , further comprising:

a second inverter stage coupled to a common gate of the first inverter stage, and wherein the second inverter stage is coupled between the high voltage source and ground.

17. The circuit of claim 16 , wherein an output voltage of the second inverter stage is at a ground voltage if the PMOS driver transistor is not driving current to the LED.

18. The circuit of claim 16 , wherein an output voltage of the second inverter stage is at the high voltage source if the PMOS driver transistor is driving current to the LED.

19. The circuit of claim 16 , wherein the second inverter stage comprising:

a second pair of PMOS transistors connected in series;

a second NMOS transistor stack, wherein the second NMOS transistor stack comprises a second pair of NMOS transistors connected in series; and

a resistor, wherein the second pair of PMOS transistors are coupled between the high voltage source and the resistor, the second NMOS transistor stack is coupled between the resistor and ground, a drain of one PMOS transistor in the second pair of PMOS transistors is coupled to the commonly coupled gates of the first inverter, and gates of the second pair of PMOS transistors and gates of the second NMOS transistor stack are commonly coupled to an inverter.

20. The circuit of claim 12 , wherein a gate voltage of the PMOS driver transistor is at the high voltage source and a gate voltage of the first PMOS transistor is at a ground voltage if the driver circuit is not driving current to the LED.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 017206 FRAME: 0666. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2016
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 038632/0662 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 12, 2008
From: AVAGO TECHNOLOGIES ECBU IP (SINGAPORE) PTE. LTD.
To: LITE-ON TECHNOLOGY CORP.
Reel/Frame 021817/0482 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 25, 2006
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES ECBU IP (SINGAPORE) PTE. LTD.
Reel/Frame 017675/0626 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2006
From: AGILENT TECHNOLOGIES, INC.
To: AVAGO TECHNOLOGIES GENERAL IP PTE. LTD.
Reel/Frame 017206/0666 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 30, 2005
From: TAI, WAI KEAT; YEO, KOK-SOON; TEO, CHEE-KEONG; ASUNCION, JOHN J. DE LEON; XU, LIAN-CHUN
To: AGILENT TECHNOLOGIES INC.
Reel/Frame 016473/0243 →