Memory DMA interface with checksum

1 . A device comprising:

a direct memory access (DMA) circuit configured to directly access a memory; and

a checksum adder configured to determine a checksum for data transferred between the DMA circuit and the memory.

2 . The device according to claim 1 wherein the DMA circuit and the checksum adder are incorporated in a cryptography circuit for performing cryptography operations, including encryption, decryption, or authentication.

3 . The device according to claim 1 wherein the DMA circuit and the checksum adder are incorporated in a semantic processor for performing data operations according to instructions from a semantic code table.

4 . The device according to claim 1 wherein the DMA circuit is configured to store the checksum in a section of the memory containing control information for the data stored in a memory.

5 . The interface according to claim 4 wherein the DMA circuit is configured to access the checksum when the data is read from the memory.

6 . The device according to claim 1 wherein the DMA circuit directly stores portions of the data to the memory and the checksum adder determines partial checksums for each of the data portions as they are stored to the memory by the DMA circuit.

7 . The device according to claim 6 wherein the DMA circuit is configured to store the partial checksums corresponding to the stored data portions in the memory.

8 . The device according to claim 1 wherein the DMA circuit selectively provides the checksum adder with the data used for determining the checksum.

9 . The device according to claim 1 wherein the DMA circuit and the checksum adder are part of a same DMA circuit.

10 . The device according to claim 1 wherein the checksum adder determines the checksum for data stored to the memory or for data loaded from the memory.

11 . A system comprising:

a semantic code table populated with direct memory access (DMA) commands;

a semantic processing unit configured to perform direct memory access operations according to the DMA commands from the semantic code table, the semantic processing unit including a checksum adder that determines a checksum for data stored during the direct memory access operations.

12 . The system of claim 11 including a cryptography circuit that performs cryptography operations including encryption, decryption, or authentication, wherein the cryptography circuit is configured to perform direct memory access operations according to the DMA commands.

13 . The system of claim 12 wherein the semantic processing unit provides the DMA commands to the cryptography circuit.

14 . The system of claim 12 wherein the cryptography circuit includes a checksum adder that determines a checksum for data stored during the direct memory access operations.

15 . The system of claim 11 including a direct execution parser causing the semantic processing unit to execute one or more of the DMA commands stored within the semantic code table.

16 . A method comprising:

performing direct memory access operations according to one or more direct memory access (DMA) commands; and

determining checksums for data stored during the direct memory access operations.

17 . The method of claim 16 including

loading the data from a device to a checksum circuit according to the DMA commands; and

storing a resulting checksum from the checksum circuit to a memory according to the DMA commands.

18 . The method of claim 16 including

loading the data from a memory to a checksum circuit according to the DMA commands; and

sending a resulting checksum from the checksum circuit to a device according to the DMA commands.

19 . The method of claim 16 including storing the checksum to a memory.

20 . The method of claim 16 including determining a plurality of partial checksums for different portions of the data during the direct memory access operations.

21 . The method of claim 16 including

selecting data to be used in determining the checksums according to the DMA commands; and

determining the checksums with the selected data.