Thin film transistor panel for liquid crystal display
View Patent ↗A thin film transistor array panel is provided, which includes: an insulating substrate; a first signal wire formed on the insulating substrate; a second signal wire formed on the insulating substrate and intersecting the first signal wire in an insulating manner; first and second pixel electrodes formed in a pixel area defined by the intersections of the first and the second signal wires and including a plurality of subareas partitioned by cutouts; a direction control electrode formed in the pixel area and including a portion overlapping at least one of the cutouts; and a first thin film transistor connected to the direction control electrode, the first signal wire, and the second signal wire.
1. A thin film transistor array panel comprising:
an insulating substrate;
a first signal wire formed on the insulating substrate;
a second signal wire formed on the insulating substrate and intersecting the first signal wire in an insulating manner;
a first pixel electrode and a second pixel electrode formed in a pixel area defined by the intersections of the first signal wire and the second signal wire;
a coupling electrode formed in the pixel area and overlapping at least one of the first pixel electrode and the second pixel electrode; and
a first thin film transistor connected with the coupling electrode, the first signal wire, and the second signal wire.
2. The thin film transistor array panel of claim 1 , wherein a voltage applied to the first pixel electrode is different from a voltage applied to the second pbcel electrode.
3. The thin film transistor array panel of claim 1 , wherein the first pixel electrode and the second pixel electrode include a plurality of sub-areas partioned by a plurality of cutouts.
4. The thin film transistor array panel of claim 3 , wherein a voltage applied to the first pixel electrode is different from a voltage applied to the second pixel electrode.
5. The thin film transistor array panel of claim 3 , wherein the cutouts of the second pixel electrode comprise a transverse cutout bisecting the second pixel electrode into upper and lower halves and a plurality of first oblique cutouts inversely symmetrical with the transverse cutout, and
wherein the cutouts of the first pixel electrode comprise a plurality of second oblique cutouts inversely symmetrical with the transverse cutout.
6. The thin film transistor array panel of claim 3 , wherein the first pixel electrode and the second pixel electrode are inversely symmetrical with the transverse cutout.
7. The thin film transistor array panel of claim 6 , further comprising:
a third signal wire intersecting the second signal wire in an insulating manner and including an electrode disposed between the first pixel electrode and the second pixel electrode.
8. The thin film transistor array panel of claim 1 , further comprising:
a second thin film transistor connected with the first pixel electrode, the first signal wire, and the second signal wire.
9. The thin film transistor array panel of claim 8 , further comprising:
a third thin film transistor connected with the first pixel electrode, the first signal wire, and the second signal wire.
10. The thin film transistor array panel of claim 1 , further comprising a third signal wire intersecting the second signal wire in an insulating manner.