IP Library Granted Patent US 8,040,168
Granted Patent B2
US 8,040,168 · App. 11/188,855 · Granted Oct 18, 2011

Charge pump circuit

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,040,168
App. No.
11/188,855
Granted
Oct 18, 2011
Kind
B2
Abstract

The charge pump circuit includes: a first switch for controlling either one of push operation and pull operation based on a first control signal; a current mirror circuit composed of a transistor different in attribute from the first switch; and a second switch composed of a transistor same in characteristic as a transistor constituting the first switch, for controlling input of a current into the current mirror circuit based on a second control. The other operation, the push operation or the pull operation, is performed with a current output from the current mirror circuit.

Claims (25)

1. A charge pump circuit for performing push-pull operation based on first and second control signals, comprising:

a first switch controlled by the first control signal;

a second switch controlled by the second control signal, the first and second switches include one type of channel transistor having substantially identical characteristics;

a first current source connected to a source of the first switch;

a second current source connected to a source of the second switch;

a current mirror circuit whose input is connected to a drain of the second switch and whose output is connected to a drain of the first switch, the current mirror circuit being inputted with a current flowing through the second switch, the current mirror circuit comprising a first transistor having a first source, first drain and first gate and a second transistor having a second source, second drain and second gate, the first drain being connected to the output of the current mirror circuit and the second drain being connected to the input of the current mirror circuit, and the first gate and the second gate being connected;

a first operational amplifier whose inverted input terminal is connected to the drain of the first switch and whose non-inverted input terminal is connected to the drain of the second switch;

a first capacitance having a first terminal and a second terminal, inserted on a negative feedback route of the first operational amplifier, the first terminal being connected to output of the first operational amplifier and the second terminal being connected to the inverted input terminal of the first operational amplifier; and

a second operational amplifier by which the first and second gates are connected, the second operational amplifier having an inverted input terminal for receiving a reference voltage and a non-inverted input terminal for receiving a voltage at the input side of the current mirror circuit, wherein:

either one of the push operation and pull operation is performed with a current flowing through the first switch, and the other operation is performed with an output current of the current mirror circuit,

an output of the second operational amplifier is connected to the first and second gates, and

the first current source, the first switch and the current mirror circuit are connected in series, and the second current source, the second switch and the current mirror circuit are connected in series.

2. The circuit of claim 1 , further comprising:

a second capacitance having a first terminal connected to the input side of the current mirror circuit and a second terminal, the second capacitance having the same capacitance value as the first capacitance.

3. A charge pump circuit for performing push-pull operation based on first and second control signals, comprising:

a first switch controlled by the first control signal;

a second switch controlled by the second control signal, the first and second switches include one type of channel transistor having substantially identical characteristics, the first and second control signals being different in phase from each other;

a current source commonly connected to sources of the first and second switches;

a current mirror circuit whose input is connected to a drain of the second switch and whose output is connected to a drain of the first switch, the current mirror being inputted with a current flowing through the second switch, the current mirror circuit comprising a first transistor having a first source, a first drain and a first gate and a second transistor having a second source, a second drain and a second gate, the first drain being connected to the output of the current mirror circuit and the second drain being connected to the input of the current mirror circuit, and the first gate and the second gate being connected;

first operational amplifier whose inverted input terminal is connected to the drain of the first switch and whose non-inverted input terminal is connected to the drain of the second switch;

a first capacitance having a first terminal and a second terminal, inserted on a negative feedback route of the first operational amplifier, the first terminal being connected to output of the first operational amplifier and the second terminal being connected to the inverted input terminal of the first operational amplifier; and

a second operational amplifier by which the first and second gates are connected, the second operational amplifier having an inverted input terminal for receiving a reference voltage and a non-inverted input terminal for receiving a voltage at the input side of the current mirror circuit, wherein:

either one of the push operation and pull operation is performed with a current flowing through the first switch, and the other operation is performed with an output current of the current mirror circuit,

an output of the second operational amplifier is connected to the first and second gates, and

the current source, the first switch and the current mirror circuit are connected in series, and the current source, the second switch and the current mirror circuit are connected in series.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2020
From: PANASONIC CORPORATION
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 052755/0917 →
CHANGE OF NAME Recorded Nov 21, 2008
From: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
To: PANASONIC CORPORATION
Reel/Frame 021897/0588 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2005
From: SAKIYAMA, SHIRO; TOKUNAGA, YUSUKE; DOSHO, SHIRO; IWATA, TORU; HIRATA, TAKASHI
To: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Reel/Frame 016815/0709 →