Generation of RTL to carry out parallel arithmetic operations
View Patent ↗Computer-implemented method and system for generating an optimized description of an arithmetic function comprising at least two of an addition, a multiplication, and a rounding operation to be carried out on a plurality of data bits in a plurality of registers of an electronic circuit, the method comprising the steps: obtaining a first description of the arithmetic function; decomposing the first description to obtain a second description comprising individual binary and logical operations on data bits, wherein the data bits are arranged to their proper place value, the second description being substantially arithmetically equivalent to the first description; obtaining a third description by parallelizing at least two of the binary and logical operations on the data bits in the second description; providing a forth description comprising operations for each data bit comprised in the third description in a hardware description language as the optimized description of the electronic circuit.
1. Computer-implemented method for generating an optimized description of an arithmetic function comprising at least two of an addition, a multiplication, and a rounding operation to be carried out on a plurality of data bits in a plurality of registers of an electronic circuit, the method comprising the steps:
obtaining a first description of the arithmetic function;
decomposing the first description to obtain a second description comprising individual binary and logical operations on data bits, wherein the data bits are arranged to their proper place value, the second description being substantially arithmetically equivalent to the first description;
obtaining a third description by parallelizing at least two of the binary and logical operations on the data bits in the second description;
providing a forth description comprising operations for each data bit comprised in the third description in a hardware description language as the optimized description of the electronic circuit.
2. The method of claim 1 , further comprising the intermediate step of assessing the arithmetic equivalence of the first and second description.
3. The method of claim 1 , wherein the parallelizing is carried out whereby the length of at least one carry chain in the second description is reduced.
4. The method of claim 3 , wherein the parallelizing is based on the combination of serial binary and/or logical operations.
5. The method of claim 4 , wherein the combination of operations comprises their concurrent execution by means of the electronic circuit.
6. The method of claim 5 , wherein at least one of the first, second or third description is a description in a hardware description language.
7. The method of claim 6 , wherein the hardware description language is RTL.
8. Computer-readable storage medium comprising program code for performing the method according to claim 1 , when loaded into a computer system.
9. Computer system for generating an optimized description of an arithmetic function comprising at least two of an addition, a multiplication, and a rounding operation to be carried out on a plurality of data bits in a plurality of registers of an electronic circuit, the system suitably programmed for the following steps:
obtaining a first description of the arithmetic function;
decomposing the first description to obtain a second description comprising individual binary and logical operations on data bits, wherein the data bits are arranged to their proper place value, the second description being substantially arithmetically equivalent to the first description;
obtaining a third description by parallelizing at least two of the binary and logical operations on the data bits in the second description;
providing a forth description comprising operations for each data bit comprised in the third description in a hardware description language as the optimized description of the electronic circuit.
10. The system of claim 9 , further suitably programmed to perform the intermediate step of assessing the arithmetic equivalence of the first and second description.
11. The system of claim 9 , suitable for parallelizing whereby the length of at least one carry chain in the second description can be reduced.
12. The system claim 11 , wherein the parallelizing is based on the combination of serial binary and/or logical operations.
13. The system of claim 12 , wherein the combination of operations comprises their concurrent execution by means of the electronic circuit.
14. The system of claim 13 , wherein at least one of the first, second or third description is a description in a hardware description language.
15. The system of claim 14 , wherein the hardware description language is RTL.