Information processing apparatus and SMI processing method thereof
View Patent ↗An information processing apparatus includes: a CPU; a controller including a signal transmission unit configured to supply an SMI (system management interrupt) signal to the CPU; a multifunctional device having a plurality of functions each potentially causing an SMI; and a plurality of signal lines provided between the controller and the multifunctional device. Each of the signal lines corresponds to one of the plurality of functions and is configured to send a notification of occurrence of an SMI event from the multifunctional device to the controller.
1. An information processing apparatus comprising:
a CPU;
a bridge circuit connected to the CPU via a hub link, the bridge circuit including a signal transmission unit configured to supply a system management interrupt (SMI) signal to the CPU;
a multifunctional device connected to the bridge circuit via a bus structure, the multifunction device having a plurality of functions each of which potentially causes an SMI; and
a plurality of signal lines of the bus structure provided between the bridge circuit and the multifunctional device, each of the signal lines corresponding to one of the plurality of functions of the multifunction device and configured to send a notification of occurrence of an SMI event from the multifunctional device to the bridge circuit.
2. The information processing apparatus as claimed in claim 1 , wherein the bridge circuit includes a register that holds information to determine an SMI cause for each of the plurality of functions.
3. The information processing apparatus as claimed in claim 2 , further comprising:
an SMI processing unit configured to acquire the information held in the register to determine whether an SMI event associated with the multifunctional device occurs when the SMI signal is supplied from the bridge circuit to the CPU.
4. The information processing apparatus as claimed in claim 1 , wherein the bus structure is a low-speed bus and the hub link is a high-speed bus.
5. An SMI processing method of an information processing apparatus, the SMI processing method comprising:
providing an information processing apparatus comprising: a CPU, a bridge circuit connected to the CPU via a hub link and having a signal transmission unit configured to supply a system management interrupt (SMI) signal to the CPU, and a multifunctional device connected to the bridge circuit via a bus structure and having a plurality of functions each of which potentially causes an SMI;
providing signal lines between the bridge circuit and the multifunctional device, each of the signal lines corresponding to one of the plurality of functions of the multifunction device and configured to send a notification of occurrence of an SMI event from the multifunctional device to the bridge circuit;
sending a notification of occurrence of the SMI event from the multifunctional device to the bridge circuit via one of the signal lines corresponding to the one of the functions in which an SMI event occurs, on the occurrence of the SMI event; and
accessing the bridge circuit to determining whether the SMI event associated with the multifunctional device occurs when the SMI signal is supplied from the bridge circuit to the CPU.
6. The SMI processing method as claimed in claim 5 , wherein the bus structure is a low-speed bus and the hub link is a high-speed bus.