Nonvolatile semiconductor memory device and method for fabricating the same
View Patent ↗A semiconductor memory device includes: first and second bit cells for storing complementary data; a scan circuit for outputting a selected data signal; a bit-cell selector receiving the output of the scan circuit and selecting one of the bit cells; and a data write controlling circuit for controlling data writing. Write paths for all the bit cells for storing “0” are not selected and data is written only in a bit cell for storing “1”, so that write operation performed in steps is achieved.
1. A nonvolatile semiconductor memory device, comprising:
a plurality of pairs of first and second bit cells for storing data;
a plurality of differential amplifiers each receiving, as complementary inputs, information from an associated one of the first bit cells and information from an associated one of the second bit cells and amplifying a difference between the inputs; and
a bit-cell selector receiving the data and controlled to select one of the first and second bit cells according to an input signal.
2. The nonvolatile semiconductor memory device of claim 1 , wherein in the selection of one of the first and second bit cells by the bit-cell selector, whether the data is written in the selected bit cell or not is determined according to the value of the data input to the bit-cell selector.
3. The nonvolatile semiconductor memory device of claim 1 , further comprising a write controlling MOS transistor having a gate electrode to which an output from the bit-cell selector is input,
wherein each of the first and second bit cells includes a nonvolatile cell transistor having a floating gate, and
in write operation, the data is written by turning the write controlling MOS transistor ON so as to inject electrons in the floating gate.
4. The nonvolatile semiconductor memory device of claim 1 , wherein the nonvolatile semiconductor memory device further comprises a plurality of first shift registers connected in series and used for inputting the data to the bit-cell selector.
5. The nonvolatile semiconductor memory device of claim 4 , further comprising a data write controlling circuit receiving an output from the bit-cell selector and enabling and disabling writing of the data according to a first control signal.
6. The nonvolatile semiconductor memory device of claim 5 , further comprising a second shift register connected to the first shift registers in series and outputting the input signal for controlling the bit-cell selector.
7. The nonvolatile semiconductor memory device of claim 4 , further comprising:
a third shift register connected to the first shift registers in series and outputting the input signal for controlling the bit-cell selector; and
a write controlling circuit receiving an output from the third shift register and enabling and disabling writing of the data according to a second control signal.
8. The nonvolatile semiconductor memory device of claim 1 , wherein each of the first and second bit cells includes two MOS transistors of a one-layer polysilicon type having respective gate electrodes connected to each other.
9. A method for fabricating a nonvolatile semiconductor memory device including a plurality of pairs of first and second bit cells for storing data, differential amplifiers each receiving, as complementary inputs, information from an associated one of the first bit cells and information from an associated one of the second bit cells and amplifying a difference between the inputs, a bit-cell selector receiving the data and controlled to select one of the first and second bit cells according to an input signal, and a plurality of shift registers connected in series, associated with the respective pairs of first and second bit cells and used for inputting the data to the bit-cell selector,
the method comprising the steps of:
setting data to be written for one of the first and second bit cells associated with a bit having a fixed length predetermined according to the number of inputs of clock signals for controlling the shift registers, and setting data having a fixed value for the other bit cells associated with bits other than the fixed-length bit, thereby writing the data to be written in said one of the first and second bit cells; and
shifting the fixed-length bit to a next fixed-length bit and writing the data to be written in another bit cell associated with the next fixed-length bit.