Method for automated at-speed testing of high serial pin count multiple gigabit per second devices
View Patent ↗A test head performs at-speed testing of high serial pin count gigabit per second (GBPS) devices. The test head includes a device under test (DUT) coupled to a first portion of the test head and a rider board coupled to the DUT. The rider board includes a first signal path including switching matrices coupled to the DUT, a second signal path including bit error rate testing (BERT) engines, each of the BERT engines being coupled to each other, corresponding ones of the switching matrices, and to the DUT, and a third signal path including Ethernet testing circuits coupled to the DUT. The BERT engines allow for routing of a test signal from any of the switching matrices to any other switching matrix (e.g., between non-adjacent switching matrices).
1. A method for performing at-speed testing of high serial pin count gigabit per second (GBPS) devices, comprising:
coupling a device under test (DUT) to a test head; and
coupling a rider board to the DUT, such that the rider board forms,
a first signal path arranged as a first ring architecture including switching matrices coupled to the DUT,
a second signal pather arranged as a second ring architecture including bit error rate testing (BERT) devices, each of the BERT engines being coupled to a corresponding switch matrix within the switching matrices, and to the DUT, and
a third signal path including Ethernet testing circuits coupled to the DUT.
2. The method of claim 1 , further comprising:
routing a test signal in the second signal path between the DUT and the rider board in a range of about 400 Megabits per second (MBPS) to about 4 GPBS.
3. The method of claim 1 , wherein the BERT engines allow for 8000 words/port of source memory and/or capture/compare memory.
4. The method of claim 1 , further comprising:
using the BERT engines as a source of a test signal.
5. The method of claim 1 , further comprising:
using the BERT engines to capture a test signal.
6. The method of claim 1 , further comprising:
using the BERT engines to compare a test signal to a desired result.
7. The method of claim 1 , further comprising:
coupling each of the BERT engines to a respective clock on the rider board.
8. The method of claim 1 , further comprising:
using the BERT engines to generate and/or monitor at least one of 7 th , 15 th , 23 rd , and 31 st order pseudo random bit sequences.
9. The method of claim 1 , further comprising:
using the BERT engines to continuously reprogram in real-time.
10. The method of claim 1 , wherein the first signal path allows for at-speed testing of analog test signals of up to or over about 8 GBPS.
11. The method of claim 1 , wherein the second signal path allows for at-speed testing of digital test signals up to about 4 GBPS.
12. The method of claim 1 , further comprising:
using the BERT engines to route a test signal from any of the switching matrices to any other switching matrix.
13. The method of claim 1 , further comprising:
using the BERT engines to route test signals between non-adjacent switching matrices.