Integrated circuit chip and integrated device
View Patent ↗Embodiments provide for integrated circuit chip and device having such an integrated circuit, in which different types of pads are arranged in separate rows. In one embodiment the pads are arranged to reduce the loop inductance of corresponding signal and power supply bond wires.
1. A device, comprising:
a substrate;
an integrated circuit disposed on the substrate;
a plurality of pads arranged directly on a surface of the substrate and electrically connected to the integrated circuit, wherein the plurality of pads comprises:
a first row of pads comprising a plurality of signal pads for transmission of a signal; and
a second row of pads comprising a plurality of power supply pads for connection to a potential, wherein the first row of pads and the second row of pads are laterally separated from one another, and wherein each signal pad has a respective power supply pad to support the transmission of the respective signal through the respective signal pad;
a redistribution element arranged on the surface of the substrate and comprising a plurality of contact elements including a respective contact element for each of the signal pads and power supply pads, the redistribution element comprising a first redistribution layer and a second redistribution layer, wherein the contact elements for the first row of pads are arranged on the first redistribution layer and the contact elements for the second row of pads are arranged on the second redistribution layer; and
a plurality of conductors connecting each of the signal pads and power supply pads to its respective contact element.
2. The device of claim 1 , wherein the plurality of conductors are bond wires.
3. The device of claim 1 , wherein the respective contact elements are arranged in a manner that matches their respective signal pad and power supply pad.
4. The device of claim 1 , wherein the pads of the first and second rows are arranged in a staggered relationship relative to one another.
5. The device of claim 1 , wherein the first row of pads and the second row of pads are substantially parallel to one another.
6. The device of claim 1 , wherein the respective power supply pad for a given signal pad is that pad in the second row of pads closest to the given signal pad.
7. The device of claim 1 , wherein each of the plurality of power supply pads is for connection to a power supply potential and wherein the plurality of pads comprises a third row of pads comprising a plurality of ground pads for connection to a ground potential; wherein the first, second and third rows are laterally separated from one another and wherein each signal pad has (i) a respective power supply pad and (ii) a respective ground pad, to support the transmission of the respective signal through the respective signal pad; and wherein the plurality of conductors comprises a respective conductor coupling each of the pads in the third row to a respective contact element.
8. The device of claim 7 , wherein the pads of the first, second and third rows have substantially the same pitch so that each signal pad and its respective power supply pad and respective ground pad are linearly arranged in a direction orthogonal to the direction of the rows.
9. The device of claim 8 , wherein the plurality of conductors are bond wires.
10. The device of claim 9 , wherein the respective conductors of a given signal pad and its respective power supply pad and respective ground pad, traverse respective coplanar paths through a common plane that extends perpendicularly from the surface of the substrate.
11. A chip, comprising:
a substrate;
an integrated circuit disposed on the substrate;
a plurality of pads arranged on a surface of the substrate and electrically connected to the integrated circuit; wherein the plurality of pads comprises:
a first row of pads comprising a plurality of signal pads for transmission of a signal; wherein the plurality of signal pads in the first row are arranged with a first pitch and the plurality of power supply pads are arranged with a second pitch, the second pitch being less than the first pitch; and
a second row of pads comprising a plurality of power supply pads for connection to a potential; wherein the rows are laterally separated from one another and wherein each signal pad has a respective power supply pad to support the transmission of the respective signal through the respective signal pad; wherein the second row of pads comprises a first plurality of pads for connection to a power supply potential and a second plurality of pads for connection to a ground potential.
12. The chip of claim 11 , wherein the first and second rows of pads are substantially parallel to one another.