GPS front end having an interface with reduced data rate
View Patent ↗A radio frequency integrated circuit for a global positioning system (GPS) application mixes radio frequency GPS signals from an external source with a predetermined intermediate frequency that is less than 4f o . In one embodiment, the intermediate frequency is selected to be 1.5f o . An intermediate frequency filter then band-limits the intermediate frequency GPS signals, rolling off at a frequency in the vicinity of 2.5 MHz to achieve substantial attenuation at 3.5-4.0 MHz. An automatic gain control circuit amplifies the filtered intermediate frequency GPS signals to proper voltage levels. The amplified intermediate frequency GPS signals is then digitized by an analog-to-digital converter at a predetermined sampling rate more than twice the intermediate frequency to provide samples of a predetermined number of bits, which are then provided for base band processing by a general purpose microprocessor over an industry-standard serial bus.
1. A radio frequency integrated circuit for a global positioning system (GPS) application, comprising:
a mixer which down-converts received GPS signals to a predetermined intermediate frequency that is less than 4f o , where f o is 1.023 MHz, to produce intermediate frequency GPS signals;
an intermediate frequency filter which receives and filters the intermediate frequency GPS signals to produce filtered intermediate frequency GPS signals;
an automatic gain control circuit which amplifies the filtered intermediate frequency GPS signals to provide amplified, filtered intermediate frequency GPS signals;
an analog-to-digital converter which digitizes the amplified, filtered intermediate frequency GPS signals at a predetermined sampling rate to provide samples of a predetermined number of bits; and
an interface which provides the samples to a base band processor over a shared serial bus, wherein the radio frequency integrated circuit (RFIC) is configurable through the serial bus into: a) an ON state wherein the RFIC controls the serial bus to provide the samples to the base band processor, and b) a STANDBY state wherein the RFIC does not control the serial bus, and wherein the base band processor is a general-purpose microprocessor.
2. A radio frequency integrated circuit as in claim 1 , further comprising a calibration circuit for setting the pass band of the intermediate frequency filter.
3. A radio frequency integrated circuit as in claim 1 , wherein the mixer comprises an image reject mixer.
4. A radio frequency integrated circuit as in claim 1 , wherein a product of the predetermined sampling rate and the predetermined number of bits is less than or equal to a data rate of the serial bus.
5. A radio frequency integrated circuit as in claim 1 , wherein the predetermined intermediate frequency is substantially 1.5f o .
6. A radio frequency integrated circuit as in claim 5 , wherein the predetermined sampling rate is substantially 6f o .
7. A radio frequency integrated circuit as in claim 5 , wherein the intermediate frequency filter rolls off in the vicinity of 2.5 MHz.
8. A radio frequency integrated circuit as in claim 6 , wherein a power spectra of the intermediate frequency filter and the analog-to-digital converter are substantially attenuated at frequencies greater than or equal to 3.5 MHz.
9. A radio frequency integrated circuit as in claim 1 , wherein the serial bus comprises a serial peripheral interface (SPI) SPI bus.
10. A radio frequency integrated circuit as in claim 1 , wherein the serial bus comprises a Multi-channel Buffered Serial Port bus.
11. A radio frequency integrated circuit as in claim 1 , wherein the radio frequency integrated circuit is further configurable into an OFF state through the serial bus.
12. A radio frequency integrated circuit as in claim 1 , wherein the baseband processor comprises a digital signal processor.
13. A method for interfacing a radio frequency integrated circuit for a global positioning system (GPS) application with a general purpose microprocessor, comprising:
receiving radio frequency GPS signals from an external source;
down-converting the GPS signals in a mixer to a predetermined intermediate frequency that is less than 4f o , where f o is 1.023 MHz, to produce intermediate frequency GPS signals;
filtering the intermediate frequency GPS signals to produce filtered intermediate frequency GPS signals;
providing an automatic gain control circuit which amplifies the filtered intermediate frequency GPS signals to produce amplified, filtered intermediate GPS signals;
digitizing the amplified, filtered intermediate frequency GPS signals at a predetermined sampling rate to provide samples of a predetermined number of bits; and
providing the samples to the general purpose microprocessor over a shared serial bus, wherein the radio frequency integrated circuit (RFIC) is configurable through the serial bus into: a) an ON state wherein the RFIC controls the serial bus to provide the samples to the base band processor, and b) a STANDBY state wherein the RFIC does not control the serial bus.
14. A method as in claim 13 , further comprising calibrating the pass band of the intermediate frequency filter.
15. A method as in claim 13 , wherein a product of the predetermined sampling rate and the predetermined number of bits is less than or equal to a data rate of the serial bus.
16. A method as in claim 13 , wherein the predetermined intermediate frequency is substantially 1.5f o .
17. A method as in claim 16 , wherein the predetermined sampling rate is substantially 6f o .
18. A method as in claim 13 , wherein the serial bus comprises an SPI bus.
19. A method as in claim 13 , wherein the serial bus comprises an Multi-channel Buffered Serial Port bus.
20. A method as in claim 13 , wherein the general purpose microprocessor comprises a digital signal processor.
21. A method as in claim 13 , further comprising configuring the radio frequency integrated circuit over the serial bus into the ON state or the STANDBY state.