IP Library Granted Patent US 7,651,900
Granted Patent B2
US 7,651,900 · App. 11/194,002 · Granted Jan 26, 2010

Mask for making polysilicon structure, method of making the same, and method of making thin film transistor using the same

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Quick Facts
Patent No.
US 7,651,900
App. No.
11/194,002
Granted
Jan 26, 2010
Kind
B2
Abstract

A mask for making a polysilicon structure includes a transmitting area that transmits light and a blocking area that has a metal layer and a semiconductor layer deposited in an alternating manner at least once. The blocking area blocks light. The mask is subject to less thermal stress from the light (e.g., a laser beam) and therefore has a longer life span compared to a conventional mask.

Claims (14)

1. A method of making a thin film transistor substrate comprising:

forming an amorphous silicon layer on an insulating substrate;

forming a polysilicon layer by irradiating the amorphous silicon layer with a laser beam through a mask for crystallization, wherein the mask comprises a transmitting area transmitting light and a blocking area that has a metal layer and a semiconductor layer deposited in an alternating manner at least once starting with the metal layer and blocking the light, wherein the mask is disposed such that the laser beam reaches the metal layer before the semiconductor layer, and wherein the crystallization is performed by sequential lateral solidification method;

forming a gate insulating layer on the polysilicon layer;

forming a gate electrode on the gate insulating layer over the polysilicon layer;

forming an inter layer dielectric having contact holes to expose a part of the polysilicon layer on the gate electrode; and

forming a source electrode and a drain electrode connected to the part of the polysilicon, respectively, through the contact hole.

2. The method according to claim 1 , wherein the transmitting area comprises a row of slits.

3. The method according to claim 2 , wherein the transmitting area comprises multiple rows of slits.

4. The method according to claim 3 , wherein the rows of slits are parallel to each other.

5. The method according to claim 4 , wherein the slits in neighboring rows are arranged in a staggered manner.

6. The method according to claim 1 , wherein the metal layer is a molybdenum layer.

7. The method according to claim 1 , wherein the semiconductor layer is a silicon layer.

8. The method according to claim 1 , wherein the semiconductor layer in the blocking area is at least twice as thick as the metal layer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 20, 2012
From: SAMSUNG ELECTRONICS CO., LTD.
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 028991/0808 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 28, 2005
From: KIM, DONG-BYUM
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 016833/0227 →