Dynamic soft-error-rate discrimination via in-situ self-sensing coupled with parity-space detection
View Patent ↗A system that facilitates distinguishing between soft errors and the onset of hardware degradation in a computer system. During operation, the system receives notifications of correctable-error events from a plurality of memory components. The system then averages numbers of correctable-error events from the plurality of memory components to generate an average number of correctable-error events across the plurality of memory components. The system subtracts the number of correctable-error events for a given memory component in a given time interval from the average number of correctable-error events to generate a residual number of correctable-error events for the given memory component in the given time interval.
1. A method for distinguishing between soft errors and the onset of hardware degradation in a computer system, comprising:
receiving notifications of correctable-error events from a plurality of memory components;
averaging numbers of correctable-error events from the plurality of memory components to generate an average number of correctable-error events across the plurality of memory components; and
for a given memory component, subtracting the number of correctable-error events for the given memory component in a given time interval from the average number of correctable-error events to generate a residual number of correctable-error events for the given memory component in the given time interval.
2. The method of claim 1 , wherein the method further comprises:
determining if the residual number of correctable-error events for a given memory component in a given time interval exceeds a threshold; and
if so, generating a warning message.
3. The method of claim 1 , wherein the method further comprises:
determining if a time-series of residuals for a given memory component is a stationary white-noise time-series with a zero mean; and
if so, determining that the time-series does not indicate the onset of hardware degradation for the given memory component.
4. The method of claim 3 , wherein the method further comprises:
determining if the time-series of the residuals for a given memory component is non-zero; and
if so, determining that the time-series indicates the onset of hardware degradation for the given memory component.
5. The method of claim 1 , wherein the method further comprises using a sequential probability ratio test to evaluate the residuals for the given memory component to generate quantitative and configurable false-alarm and missed-alarm probabilities for the given memory component.
6. The method of claim 1 , wherein the memory components can include banks of memory or cache memories.
7. The method of claim 1 , wherein the plurality of memory components are located within one computer system.
8. The method of claim 1 , wherein the plurality of memory components are distributed across a plurality of computer systems.