Semiconductor device and method of manufacturing the same
View Patent ↗A lateral MOSFET and a method of forming thereof includes a p-type semiconductor substrate, a first n-type well in the surface portion of the semiconductor substrate, an n + -type drain region in the first n-type well, a p-type well in the first n-type well, an n + -type source region in the p-type well, a gate oxide film on the portion of the p-type well between the n + -type source region and the first n-type well, a gate electrode on the gate oxide film, and a second n-type well containing the p-type well therein to increase the n-type impurity concentration in the vicinity of the junction between the p-type well and the first n-type well beneath the gate and to increase the impurity amount and the thickness of the n-type semiconductor region beneath the p-type well. The first and second n-type wells can be overlapping or formed continuous or contiguous with each other. The lateral MOSFET exhibits a high punch-through breakdown voltage suitable for a high-side switch.
1. A semiconductor device comprising:
a semiconductor layer of a first conductivity type;
a first semiconductor region of a second conductivity type in the surface portion of the semiconductor layer;
a drain region of the second conductivity type in the first semiconductor region;
a second semiconductor region of the second conductivity type in contact with or overlapping with the first semiconductor region;
a channel region of the first conductivity type in the surface portion of the second semiconductor region;
a source region of the second conductivity type in the channel region; and
a gate electrode above the channel region between the source region and the first semiconductor region with a gate insulator film interposed therebetween,
wherein the net total impurity amount in the first semiconductor region is smaller than the net total impurity amount in the second semiconductor region, and
wherein, under the gate electrode between the drain region and the channel region, an impurity concentration in a channel region side of the second semiconductor region is higher than the impurity concentration of the first semiconductor region.
2. The semiconductor device according to claim 1 , wherein the channel region is spaced apart from the drain region.
3. The semiconductor device according to claim 1 , wherein the second semiconductor region is doped more heavily than the first semiconductor region.
4. The semiconductor device according to claim 1 , wherein the first semiconductor region is contiguous or continuous with the second semiconductor region.
5. The semiconductor device according to claim 1 , wherein the net total impurity amount in the first semiconductor region is larger on the side of the drain region than on the side of the second semiconductor region.
6. The semiconductor device according to claim 1 , further including a thick insulator layer for relaxing an electric field on a portion of the first semiconductor region between the drain region and the channel region, the portion of the first semiconductor region being spaced apart from the channel region.
7. The semiconductor device according to claim 1 , wherein the net total impurity amount per unit area in the first semiconductor region is between 0.5×10 12 cm −2 and 3.0×10 12 cm −2 .
8. A method of manufacturing the semiconductor device comprising:
a semiconductor layer of a first conductivity type;
a first semiconductor region of a second conductivity type in the surface portion of the semiconductor layer;
a drain region of the second conductivity type in the first semiconductor region;
a second semiconductor region of the second conductivity type in contact with or overlapping with the first semiconductor region;
a channel region of the first conductivity type in the surface portion of the second semiconductor region;
a source region of the second conductivity type in the surface portion of the channel region;
a contact region of the first conductivity type in the surface portion of the channel region and contiguous with the source region;
a source electrode in contact with both the source region and the contact region; and
a gate electrode above the channel region between the source region and the first semiconductor region with a gate insulator film interposed therebetween,
wherein the net total impurity amount in the first semiconductor region is smaller than the net total impurity amount in the second semiconductor region, and
wherein, under the gate electrode between the drain region and the channel region, an impurity concentration in a channel region side of the second semiconductor region is higher than the impurity concentration of the first semiconductor region,
the method comprising the steps of:
forming thick insulator films selectively on the surface of the semiconductor layer; implanting impurity ions of the second conductivity type in an self-aligning manner into portions of the semiconductor layer, to form the first semiconductor region and the second semiconductor region, using the thick insulator films as ion implantation masks;
covering the portion of the semiconductor layer where the first semiconductor region is to be formed, with a mask film; and
implanting impurity ions of the second conductivity type in an self-aligning manner into the portion of the semiconductor layer where the second semiconductor region is to be formed, using the thick insulator films and the mask film as ion implantation masks.
9. A method of manufacturing a semiconductor device comprising:
a semiconductor layer of a first conductivity type;
a first semiconductor region of a second conductivity type in the surface portion of the semiconductor layer;
a drain region of the second conductivity type in the first semiconductor region;
a second semiconductor region of the second conductivity type in contact with or overlapping with the first semiconductor region;
a channel region of the first conductivity type in the surface portion of the second semiconductor region;
a source region of the second conductivity type in the surface portion of the channel region;
a contact region of the first conductivity type in the surface portion of the channel region and contiguous with the source region;
a source electrode in contact with both the source region and the contact region; and
a gate electrode above the channel region between the source region and the first semiconductor region with a gate insulator film interposed therebetween,
wherein the net total impurity amount in the first semiconductor region is smaller than the net total impurity amount in the second semiconductor region, and
wherein, under the gate electrode between the drain region and the channel region, an impurity concentration in a channel region side of the second semiconductor region is higher than the impurity concentration of the first semiconductor region,
the method comprising the steps of:
forming a thick insulator film selectively on the surface of the semiconductor layer;
covering portions of the semiconductor layer where the first semiconductor region and the second semiconductor region are to be formed, with a mask film having openings; and
implanting impurity ions of the second conductivity type in an self-aligning manner into the portions of the semiconductor layer where the first semiconductor region and the second semiconductor region are to be formed, using the thick insulator film and the mask film as ion implantation masks.
10. The method according to claim 9 , wherein an opening shape in the portion of the mask film for forming the first semiconductor region is different from an opening shape in the portion of the mask film for forming the second semiconductor region.
11. The method according to claim 10 , wherein the portion of the mask film for forming the first semiconductor region has a plurality of openings.