IP Library Granted Patent US 10,102,350
Granted Patent B1
US 10,102,350 · App. 11/197,561 · Granted Oct 16, 2018

System and method for protecting data stored in the control registers of an integrated circuit

Inventors: Zheng Liu (Sunnyvale, CA); Jiande Jiang (San Jose, CA)
Assignee: Entropic Communications, LLC
G06F21/10
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,102,350
App. No.
11/197,561
Granted
Oct 16, 2018
Kind
B1
Abstract

The present invention provides a system and method for protecting data stored in the control registers of an integrated circuit, such as a television chip. The system and method use one or more selectively activated read protection modules to prevent the control registers from being read unless a predetermined key or password is entered. The password or key may be stored in password registers within the chip. A key access generator will enable read access of the control registers if correct values are written to the appropriate password registers. The key access generator may enable read access for a predetermined period of time or until it receives another input.

Claims (27)

1. A system, comprising:

a central processing unit (CPU); and

a digital television chip operable to prevent unauthorized access to at least one performance parameter, wherein the digital television chip comprises:

a video processing component configured to receive combined video data, customize a display picture quality according to the combined video data, and communicate a plurality of video outputs, wherein at least one video output of the plurality of video outputs is in an analog format and at least one video output of the plurality of video outputs is in a digital format;

at least one control register associated with the video processing component, and having a value associated with said at least one performance parameter that controls operation of the video processing component; and

a read protection component configured to prevent the value associated with said at least one performance parameter from being read out of the at least one control register by the CPU, wherein the read protection component is configured to prevent data from being read out of the at least one control register to a port while simultaneously allowing data to be read out of the at least one control register to the video processing component, and wherein said read protection component comprises a serial port and a parallel port, and wherein access, to said at least one performance parameter, via said serial port is selectably enabled and independent of whether access, to said at least one performance parameter, via said parallel port is enabled.

2. The system of claim 1 , wherein the read protection component comprises a key access generator that is configured to:

receive input values;

compare the input values to a predetermined key; and

if the input values are equal to the predetermined key, disable the read protection component to allow the data stored in the at least one control register to be read;

and wherein the read protection component comprises an AND gate, and wherein an input to the AND gate is an output from the key access generator and another input to the AND gate is a read signal.

3. The system of claim 1 , wherein the read protection component is configured to lock access to the at least one control register.

4. The system of claim 1 , wherein the read protection component is configured to unlock access to the at least one control register, to allow controlling of the video processing component through changes to the at least one performance parameter.

5. The system of claim 2 , wherein the predetermined key comprises a predetermined set of values written to a predetermined set of registers of the control registers.

6. A system, comprising:

a central processing unit (CPU); and

a digital television chip operable to prevent unauthorized access to at least one performance parameter, wherein the digital television chip comprises:

an audio processing component configured to receive combined audio data, customize an audio quality according to the combined audio data, and communicate a plurality of audio outputs;

at least one control register associated with the audio processing component, and having a value associated with at least one performance parameter that controls the operation of the audio processing component; and

a read protection component configured to prevent the value associated with said at least one performance parameter from being read out of the at least one control register by the CPU, wherein the read protection component is configured to prevent data from being read out of the at least one control register to a port while simultaneously allowing data to be read out of the at least one control register to the audio processing component, and wherein said read protection component comprises a serial port and a parallel port, and wherein access, to said at least one performance parameter, via said serial port is selectably enabled and independent of whether access, to said at least one performance parameter, via said parallel port is enabled.

7. The system of claim 6 , wherein the read protection component comprises a key access generator that is configured to:

receive input values,

compare the input values to a predetermined key; and

if the input values are equal to the predetermined key, disable the read protection component to allow the data stored in the at least one control register to be read.

8. The system of claim 7 , wherein the read protection component is configured to lock access to the at least one control register.

9. The system of claim 8 , wherein the read protection component is configured to unlock access to the at least one control register, to allow controlling of the audio processing component through changes to the at least one parameter stored in the at least one control register.

10. The system of claim 7 , wherein the predetermined key comprises a predetermined set of values written to a predetermined set of registers of the control registers.

Assignments (9)
SECURITY AGREEMENT Recorded Jul 9, 2021
From: MAXLINEAR, INC.; MAXLINEAR COMMUNICATIONS, LLC; EXAR CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 056816/0089 →
RELEASE OF SECURITY INTEREST Recorded Jun 23, 2021
From: MUFG UNION BANK, N.A.
To: MAXLINEAR, INC.; EXAR CORPORATION; MAXLINEAR COMMUNICATIONS LLC
Reel/Frame 056656/0204 →
SUCCESSION OF AGENCY (REEL 042453 / FRAME 0001) Recorded Jul 1, 2020
From: JPMORGAN CHASE BANK, N.A.
To: MUFG UNION BANK, N.A.
Reel/Frame 053115/0842 →
SECURITY AGREEMENT Recorded May 12, 2017
From: MAXLINEAR, INC.; ENTROPIC COMMUNICATIONS, LLC (F/K/A ENTROPIC COMMUNICATIONS, INC.); EXAR CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 042453/0001 →
MERGER AND CHANGE OF NAME Recorded May 18, 2015
From: ENTROPIC COMMUNICATIONS, INC.; EXCALIBUR SUBSIDIARY, LLC; ENTROPIC COMMUNICATIONS, LLC
To: ENTROPIC COMMUNICATIONS, LLC
Reel/Frame 035706/0188 →
MERGER AND CHANGE OF NAME Recorded May 15, 2015
From: EXCALIBUR ACQUISITION CORPORATION; ENTROPIC COMMUNICATIONS, INC.; ENTROPIC COMMUNICATIONS, INC.
To: ENTROPIC COMMUNICATIONS, INC.
Reel/Frame 035704/0504 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 3, 2012
From: TRIDENT MICROSYSTEMS, INC.; TRIDENT MICROSYSTEMS (FAR EAST) LTD.
To: ENTROPIC COMMUNICATIONS, INC.
Reel/Frame 028153/0530 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 15, 2007
From: TRIDENT TECHNOLOGIES, INC.
To: TRIDENT MICROSYSTEMS (FAR EAST) LTD.
Reel/Frame 018895/0575 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 12, 2005
From: LUI, ZHENG; JIANG, JIANDE
To: TRIDENT TECHNOLOGIES, INC.
Reel/Frame 016768/0717 →