Partially patterned lead frames and methods of making and using the same in semiconductor packaging
View Patent ↗A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging (CSP) lead-counts is accomplished by performing a major portion of the manufacturing process steps with a partially patterned strip of metal formed into a web-like lead frame on one side, so that the web-like lead frame, which is solid and flat on the other side is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both at the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is encapsulated. The resultant package being electrically isolated enables strip testing and reliable singulation without having to cut into any additional metal.
1. A method of forming a partially patterned lead frame comprising the steps of:
forming a metallic film having a top surface and a uniform preplated bottom surface; and
partial patterning the film from the top surface, but not entirely through the bottom surface of the film in a first region to form a webbed structure interconnecting a second region not partially patterned from the top surface;
wherein the second region has (a) a chip pad area for supporting an integrated circuit (IC) chip and, (b) a plurality of electrical leads electrically separated from the pad area, the leads for providing electrical connections to the IC chip.
2. The method according to claim 1 , wherein the film comprises copper or a copper alloy.
3. The method according to claim 1 , wherein the film has a thickness of equal to or greater than 0.05 mm.
4. The method according to claim 1 , wherein the partial patterning comprises removing about 25% to 90% of the thickness of the film.
5. The method according to claim 1 , further comprising the step of pre-plating the top surface of the film.
6. The method according to claim 1 , further comprising the step of pre-plating the top surface and the bottom surface of the film.
7. The method according to claim 5 or 6 , wherein the pre-plating of the top surface comprises using a wire bondable material.
8. The method according to claim 7 , wherein the bondable material comprises Ni/Pd/Au or Ag.
9. The method according to claim 6 , wherein the pre-plating of the bottom surface involves using a solderable material.
10. The method according to claim 9 , wherein the solderable material is Sn/Pb, lead-free solder, immersion-tin, electroless-nickel or Au-strike.
11. The method according to claim 1 , wherein the first region has exposed vertical walls having irregular shapes to form interlocking surfaces when engaged with other materials.
12. The method according to claim 1 , wherein the chip pad area comprises the end portions of the electrical leads to accommodate the solder bump joining of a flip-chip.