Method of making a multi-bit-cell flash memory

1. A method of managing a flash memory, comprising the steps of:

(a) selecting a value of a number N≧3 of respective bits of data to be stored in each of a plurality of cells of at least a portion of the flash memory;

(b) reserving a single other cell of the flash memory to use as a flag cell to represent a value of how many of said N bits are stored in each said cell of said plurality of cells; and

(c) successively, for each value of n between 1 and N:

(i) programming each said cell of said plurality of cells to represent a respective n bits of said data, and

(ii) programming said flag cell to represent n;

wherein said successive programming of each said cell of said plurality of cells and of said flag cell is completed without erasing any of said cells of said plurality of cells and without erasing said flag cell until after said cells of said plurality of cells and said flag cell have been programmed at n=N.

2. The method of claim 1 , wherein said at least portion of the flash memory is a block of the flash memory.

3. The method of claim 1 , wherein said at least portion of the flash memory is a page of the flash memory.

4. The method of claim 1 , wherein N is selected equal to 3.

5. The method of claim 1 , wherein N is selected equal to 4.

6. A memory device comprising:

(a) a flash memory including at least one block, each said at least one block including at least one page, each said at least one page including a plurality of cells; and

(b) a flash memory controller operative, for a portion of said flash memory selected from the group consisting of one of said at least one block and one of said at least one page of one of said at least one block:

(i) to select a value of a number N≧3 of respective bits of data to be stored in each of a plurality of cells of said portion,

(ii) to reserve a single other cell of said portion to use as a flag cell to represent a value of how many of said N bits are stored in each said cell of said plurality of cells, and

(iii) successively, for each value of n between 1 and N:

(A) to program each said cell of said plurality of cells to represent a first respective n bits of said data, and

(B) to program said flag cell to represent n;

wherein said flash memory controller is operative to complete said successive programming of said cells of said plurality of cells and of said flag cell without erasing said cells of said plurality of cells and without erasing said flag cell until after said cells of said plurality of cells and said flag cell have been programmed at n=N.

7. The memory device of claim 6 , wherein N=3.

8. The memory device of claim 6 , wherein N=4.

9. A system comprising:

(a) a flash memory including at least one block, each said at least one block including at least one page, each said at least one page including a plurality of cells;

(b) a non-volatile memory for storing program code operative, for a portion of said flash memory selected from the group consisting of one of said at least one block and one of said at least one page of one of said at least one block to:

i) select a value of a number N≧3 of respective bits of data to be stored in each of a plurality of cells of said portion,

(ii) reserve a single other cell of said portion to use as a flag cell to represent a value of how many of said N bits are stored in each said cell of said plurality of cells of said portion, and

(iii) successively, for each value of n between 1 and N:

(A) program each said cell of said plurality of cells of said portion to represent a respective n bits of said data, and

(B) program said flag cell to represent n; and

(c) a processor for executing said program code;

wherein said program code is for completing said successive programming of said cells of said plurality of cells of said portion and of said flag cell without erasing said cells of said plurality of cells of said portion and without erasing said flag cell until after said cells of said plurality of cells of said portion and said flag cell have been programmed at n=N.

10. The system of claim 9 , wherein N=3.

11. The system of claim 9 , wherein N=4.

12. A computer-readable storage medium having computer-readable code embedded on the computer-readable storage medium, the computer-readable code for managing a flash memory that includes at least one block, each at least one block including at least one page, each at least one page including a plurality of cells, the computer-readable code comprising program code operative, for a portion of the flash memory selected from the group consisting of one of the at least one block and one of the at least one page of one of the at least one block to:

(a) select a value of a number N≧3 of respective bits of data to be stored in each of a plurality of cells of the portion;

(b) reserve a single other cell of the portion to use as a flag cell to represent a value of how many of said N bits are stored in each cell of the plurality of cells of the portion; and

(c) successively, for each value of n between 1 and N:

(i) program each cell of the plurality of cells of the portion to represent a respective n bits of said data, and

(ii) program said flag cell to represent n;

wherein said program code is for completing said successive programming of said cells of said plurality of cells of the portion and of said flag cell without erasing said cells of said plurality of cells of the portion and without erasing said flag cell until after said cells of said plurality of cells of the portion and said flag cell have been programmed at n=N.

13. The computer-readable storage medium of claim 12 , wherein N=3.

14. The computer-readable storage medium of claim 12 , wherein N=4.

15. A method of managing a non-volatile array of storage elements individually having a storage window divisible into a plurality of defined ranges of storage levels representative of at least one bit of data and which are separated from one another, the method comprising the steps of:

(a) selecting a number N≧3 of bits to be represented by the defined ranges of the storage levels of each of a plurality of the storage elements of at least a portion of the non-volatile, array;

(b) reserving a single other storage element to use as a flag storage element to represent a value of how many of the N bits are stored in each storage element of said plurality of the storage elements; and

(c) successively, for each value of n between 1 and N:

(i) setting each storage element of said plurality of the storage elements to represent a respective n bits of the data, and

(ii) setting said flag storage element to represent n;

wherein said successive setting of said storage elements of said plurality of the storage elements and of said flag storage element is completed without erasing any of said storage elements of said plurality of the storage elements and without erasing said flag storage element until after said storage elements of said plurality of the storage elements and said flag storage element have been set at n=N.

16. The method of claim 15 , wherein N is selected equal to 3.

17. The method of claim 15 , wherein N is selected equal to 4.

18. A memory device comprising:

(a) a non-volatile array of storage elements individually having a storage window divisible into a plurality of defined ranges of storage levels representative of at least one bit of data and which are separated from one another; and

(b) a controller for:

(i) selecting a number N≧3 of bits to be represented by the defined ranges of the storage levels of each of a plurality of said storage elements of at least a portion of the non-volatile array,

(ii) reserving a single other said storage element to use as a flag storage element to represent a value of how many of said N bits are stored in each said storage element of said plurality of said storage elements, and

(iii) successively, for each value of n between 1 and N:

(A) setting each said storage element of said plurality of said storage elements to represent a first respective n bits of said data, and

(B) setting said flag storage element to represent n;

wherein said controller is operative to complete said successive setting of said storage elements of said plurality of said storage elements and of said flag storage element without erasing said storage elements of said plurality of said storage elements and without erasing said flag storage element until after said storage element of said plurality of said storage elements and said flag storage element have been set at n=N.

19. The memory device of claim 18 , wherein N=3.

20. The memory device of claim 18 , wherein N=4.

21. A system comprising:

(a) a non-volatile array of storage elements individually having a storage window divisible into a plurality of defined ranges of storage levels representative of at least one bit of data and which are separated from one another;

(b) a non-volatile memory for storing program code for:

(i) selecting a number N≧3 of bits to be represented by the defined ranges of the storage levels of each of a plurality of said storage elements of at least a portion of said non-volatile array,

(ii) reserving a single other said storage element to use as a flag storage element to represent a value of how many of said N bits are stored in each said storage element of said plurality of said storage elements, and

(iii) successively, for each value of n between 1 and N:

(A) setting each said storage element of said plurality of said storage elements to represent a respective n bits of said data, and

(B) setting said flag storage element to represent n; and

(c) a processor for executing said program code;

wherein said program code is for completing said successive setting of said storage elements of said plurality of said storage elements and of said flag storage element without erasing said storage elements of said plurality of said storage elements and without erasing said flag storage element until after said storage elements of said plurality of said storage elements and said flag storage element have been set at n=N.

22. The system of claim 21 , wherein N=3.

23. The system of claim 21 , wherein N=4.

24. A computer-readable storage medium having computer-readable code embedded on the computer-readable storage medium, the computer-readable code for managing a non-volatile array of storage elements individually having a storage window divisible into a plurality of defined ranges of storage levels representative of at least one bit of data and which are separated from one another, the computer-readable code comprising:

(a) program code for selecting a number N≧3 of bits to be represented by the defined ranges of the storage levels of each of a plurality of the storage elements of at least a portion of the non-volatile array;

(b) program code for reserving a single other storage element to use as a flag storage element to represent a value of how many of the N bits are stored in each said storage element of said plurality of the storage elements; and

(c) program code for successively, for each value of n between 1 and N:

(i) setting each said storage element of said plurality of the storage elements to represent a respective n bits of said data, and

(ii) setting said flag storage element to represent n;

wherein said program code is for completing said successive setting of said storage elements of said plurality of the storage elements and of said flag storage element without erasing said storage elements of said plurality of the storage elements and without erasing said flag storage element until after said storage elements of said plurality of the storage elements and said flag storage element have been set at n=N.

25. The computer-readable storage medium of claim 24 , wherein N=3.

26. The computer-readable storage medium of claim 24 , wherein N=4.