Frequency synthesizer for dual mode receiver
View Patent ↗In a portable dual mode receiver circuit, a dual modulus clock system is provided which can, by selective use of integer division on a multiplied master clock, select specific channels with two different channel spacings in several different bands, providing power and space savings and achieving simplicity of operation.
1. In a portable dual mode receiver circuit, a clock system comprising:
a baseband clock circuit;
a multiplier circuit coupled to the baseband clock circuit for multiplying a baseband clock by a multiplier value to a master clock frequency which has as factors a first integer divider value of a first channel spacing clock signal of a first band, and a second integer divider value of a second channel spacing clock signal of a second band;
a programmable reference divider coupled to receive a clock signal of said master clock frequency, said programmable divider selectively dividing said master clock frequency by said first integer divider value of said first band or by said second integer divider value of said second band to produce respectively said first channel spacing clock signal and said second channel spacing clock signal;
a voltage controlled oscillator (VCO) coupled to receive a phase error signal for generating a frequency controlled analog radio frequency (RF) signal at a desired frequency for system output;
a programmable VCO divider circuit coupled to receive said analog RF signal, said programmable VCO divider circuit dividing a frequency of said analog RF signal by a first channel integer when said programmable reference divider produces said first channel spacing clock signal, and dividing the frequency of said analog RF signal by a second channel integer when said programmable reference divider produces said second channel spacing clock signal, and producing a digital feedback signal; and,
a digital phase detector coupled to receive an output of said programmable reference divider to detect phases of said first channel spacing clock signal and said second channel spacing clock signal, said digital phase detector also having as a reference input the digital feedback signal, said digital phase detector producing as an output an analog phase error signal in a form of a steering voltage.
2. The circuit according to claim 1 wherein
a baseband clock frequency is 13 MHz;
said multiplier value is 3 such that said master clock frequency is 39 MHz;
said first integer divider value is 1300 for producing a channel spacing increment of 30 kHz; and wherein
said second integer divider value is 195 for producing a channel spacing increment of 200 kHz.
3. The circuit according to claim 2 wherein
said first channel integer is nominally selectable between 25,000 and 30,000; and wherein
said second channel integer is nominally selectable between 4,000 and 10,000.
4. The circuit according to claim 3 wherein
said first channel integer is nominally 28,000; and wherein
said second channel integer is nominally 4,500.
5. In a portable dual mode receiver circuit, a method for selecting channels using a clock system comprising:
generating a baseband clock signal;
multiplying said baseband clock signal by a multiplier value to a master clock frequency which has as factors a first integer divider value of a first channel spacing clock signal of a first band, and a second integer divider value of a second channel spacing clock signal of a second band;
programmably dividing a clock signal of said master clock frequency selectively by said first integer divider value of said first band or by said second integer divider value of said second band to produce respectively said first channel spacing clock signal and said second channel spacing clock signal;
generating a frequency controlled analog radio frequency (RF) signal at a desired frequency for system output from a voltage controlled oscillator (VCO) coupled to receive a phase error signal; and
dividing a frequency of said analog RF signal by a first channel integer when said clock signal of said master clock frequency is divided by said first integer divider value, and dividing the frequency of said analog RF signal by a second channel integer when said clock signal of said master clock frequency is divided by said second integer divider value, and producing a digital feedback signal; and
digitally detecting phases of said first channel spacing clock signal and said second channel spacing clock signal, with respect to a reference input of the digital feedback signal, to produce as an output an analog phase error signal in a form of a steering voltage.
6. The method according to claim 5 wherein
a baseband clock frequency is 13 MHz; said multiplier value is 3 such that said master clock frequency is 39 MHz; said first integer divider value is 1300 for producing a first channel spacing increment of 30 kHz; and said second integer divider value is 195 for producing a second channel spacing increment of 200 kHz.
7. The method of claim 6 , wherein the first channel spacing increment corresponds to a GSM standard and the other second channel spacing increment corresponds to an IS-136 standard.