IP Library Granted Patent US 7,725,800
Granted Patent B2
US 7,725,800 · App. 11/198,945 · Granted May 25, 2010

Decoding techniques for correcting errors using soft information

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,725,800
App. No.
11/198,945
Granted
May 25, 2010
Kind
B2
Abstract

Two levels of error correction decoding are performed using first and second level decoders. A composite code formed by combining an inner component code and an outer component code can be used to decode the data and correct any errors. Performing two level decoding using a composite code allows the size of the inner parity block to be reduced to a single Reed-Solomon symbol while keeping a good code rate. The first level decoder generates soft information. The soft information can indicate a most likely error event for each possible syndrome value of the inner component code. The soft information can also include error metric values for each of the most likely error events. The second level decoder generates corrected syndrome values based on the soft information using the outer component code. The most likely trellis path that corresponds to the corrected syndrome values is then selected.

Claims (18)

1. A data storage apparatus that decodes encoded data to perform error correction, wherein the data storage apparatus comprises:

means for generating syndrome values for error events in an input sequence using a first error correction code;

means for generating reliability information by selecting a most likely error event for each span of a symbol in the input sequence having a minimum error metric value among the error events that have a first syndrome value, and by selecting a most likely error event for each span of the symbol in the input sequence having a minimum error metric value among the error events that have a second syndrome value;

means for applying a second error correction code to provide corrected syndrome values using the reliability information; and

means for selecting a most likely symbol corresponding to an error event having a smallest error metric value among the error events having syndrome values consistent with the corrected syndrome values.

2. The data storage apparatus defined in claim 1 further comprising:

means for generating error metric values each indicating a probability that a set of error values in the input sequence is caused by one of a set of error events.

3. The data storage apparatus defined in claim 1 wherein the means for generating syndrome values for error events in an input sequence using a first error correction code further comprises means for applying an inner component code of a composite error correction code to symbols in the input sequence.

4. The data storage apparatus defined in claim 3 wherein the means for applying a second error correction code to provide corrected syndrome values using the reliability information further comprises means for applying an outer component code of the composite error correction code to provide the corrected syndrome values using the reliability information.

5. The data storage apparatus defined in claim 1 further comprising:

means for performing error correction on the most likely symbol using a Reed-Solomon decoding technique.

6. The data storage apparatus defined in claim 1 wherein the means for applying a second error correction code to provide corrected syndrome values using the reliability information further comprises means for applying one of a low density parity check code, a block parity code, a convolutional code, and a Turbo code to provide the corrected syndrome values using the reliability information.

7. The data storage apparatus defined in claim 1 wherein the means for applying a second error correction code to provide corrected syndrome values using the reliability information further comprises:

means for grouping at least a subset of the most likely error events into potentially valid sets of the most likely error events such that each of the potentially valid sets of the most likely error events has one error event for each span of a symbol and each of the potentially valid sets of the most likely error events has syndrome values that form a codeword of the second error correction code; and

means for selecting one of the potentially valid sets of the most likely error events that has a minimum total error metric value among the potentially valid sets of the most likely error events.

8. The data storage apparatus defined in claim 1 further comprising:

means for generating most likely symbols by applying the most likely error events to symbols in the input sequence,

wherein the means for selecting a most likely symbol corresponding to an error event having a smallest error metric value among the error events having syndrome values consistent with the corrected syndrome values further comprises means for selecting the most likely symbol from among the most likely symbols such that the most likely symbol corresponds to an error event having a smallest error metric value among the error events having syndrome values consistent with the corrected syndrome values.

Assignments (8)
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 5, 2016
From: HGST NETHERLANDS B.V.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 040819/0450 →
CHANGE OF NAME Recorded Oct 25, 2012
From: HITACHI GLOBAL STORAGE TECHNOLOGIES NETHERLANDS B.V.
To: HGST NETHERLANDS B.V.
Reel/Frame 029341/0777 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2006
From: YANG, SHAOHUA; GALBRAITH, RICHARD LEO; LAKOVIC, KSENIJA; LEE, YUAN XING; OENNING, TRAVIS; PARK, JONGSEUNG; SAWAGUCHI, HIDEKI; WILSON, BRUCE A.
To: HITACHI GLOBAL TECHNOLOGIES NETHERLANDS, B.V.
Reel/Frame 017279/0288 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 5, 2005
From: YANG, SHAOHUA; GALBRAITH, RICHARD LEO; LAKOVIC, KSENIJA; LEE, YUAN XING; OENNING, TRAVIS; PARK, JONGSEUNG; SAWAGUCHI, HIDEKI; WILSON, BRUCE A.
To: HITACHI GLOBAL TECHNOLOGIES NETHERLANDS, B.V.
Reel/Frame 016874/0194 →