Data serializer
View Patent ↗A method of serializing a data stream includes passing a series of data words from a source in a first clock domain to a serializer in a second clock domain and passing valid signals from the source to the serializer indicating when each of the data words is available from the source. The serializer divides each of the data words into a plurality of portions for serial transmission. The method also includes synchronizing the serializer and the source based on the first of the valid signals.
1. An apparatus for serializing a data stream, the apparatus comprising:
a data word input;
a serial data output, wherein said data word input is wider in data bits than said serial data output;
a memory having a data input, an output select control input and an output, said data input being connected to said data word input, said output being connected to said serial data output;
a data word valid input;
a state machine having an input and an output, said state machine being connected to said data word valid input, said state machine output being connected to said output select control input of said memory, wherein a signal on said state machine output selects data in said memory for output on said memory output; and
a synchronizing latch chain connected between said data word valid input and said state machine input, said synchronizing latch chain comprising an OR gate having a first input connected to said data word valid input and a second input connected to an output of said synchronizing latch chain, said OR gate having an output connected to an input of a first latch input in said synchronizing latch chain, said output of said synchronizing latch chain being connected to said state machine input so that said synchronizing latch chain output remains asserted after said data word valid input is first asserted.
2. The apparatus of claim 1 , said state machine comprising a ring of latches in which an asserted value circulates after said data word valid input has been asserted, said state machine output comprising a plurality of select signals connected to latch outputs at various points of said ring of latches, said plurality of select signals controlling which data is output from said memory.
3. The apparatus of claim 2 , wherein ring of latches is clocked by a clock that operates at a higher speed than an external clock associated with data words appearing at said data word input, and wherein said clock and said external clock are not purposely aligned.
4. The apparatus of claim 1 , at least one latch in said synchronizing latch chain comprising a resolving latch.
5. The apparatus of claim 1 , wherein latches in said synchronizing latch chain are clocked by an internal clock that operates at a higher speed than an external clock associated with data words appearing at said data word input, and wherein said internal clock and said external clock are not purposely aligned.
6. The apparatus of claim 1 , said synchronizing latch chain further comprising an offset select multiplexer, said synchronizing latch chain output comprising an output of said offset select multiplexer, said offset select multiplexer having a plurality of inputs each connected to a latch output at a different stages of said synchronizing latch chain to select a delay between said data word valid input first being asserted and said synchronizing latch chain output being asserted.
7. The apparatus of claim 1 , said memory comprising a first-in-first-out memory comprising at least one transparent latch, wherein said state machine output periodically selects an oldest entry in said memory for output.
8. The apparatus of claim 1 , said memory comprising at least one clock input connected to said data word valid input so that data is stored in said memory at transitions of said data word valid input.
9. The apparatus of claim 1 , further comprising an output select multiplexer connected between said memory output and said serial data output, said multiplexer comprising a plurality of inputs, each of which is connected to a portion of said memory output, so that an output of said multiplexer places a portion of a data word at said memory output on said serial data output.
10. The apparatus of claim 9 , further comprising a portion select ring of latches in which an asserted value circulates after said data word valid input has been asserted, said portion select ring of latches having a plurality of outputs connected to latch outputs at various points of said portion select ring of latches, said plurality of portion select ring of latches outputs being connected to a control input of said output select multiplexer to periodically select different data word portions for output to said serial data output.