Semiconductor device with integrated flash memory and peripheral circuit and its manufacture method
View Patent ↗A non-volatile semiconductor memory device includes: a non-volatile memory area including gate electrodes, each including stack of a floating gate, an inter-electrode insulating film and a control gate, and having first insulating side walls formed on side walls of the gate electrode; a peripheral circuit area including single-layer gate electrodes made of the same layer as the control gate; and a first border area including: a first isolation region formed in the semiconductor substrate for isolating the non-volatile memory area and peripheral circuit area; a first conductive pattern including a portion made of the same layer as the control gate and formed above the isolation region; and a first redundant insulating side wall made of the same layer as the first insulating side wall and formed on the side wall of the first conductive pattern on the side of the non-volatile memory area.
1. A non-volatile semiconductor memory device comprising:
a semiconductor substrate;
a non-volatile memory area including a non-volatile memory cell having a gate electrode including a floating gate, an inter-electrode insulating film and a control gate stacked above said semiconductor substrate and having first insulating side walls formed on side walls of said gate electrode;
wherein said control gate comprises a first material and said first insulating side walls comprises a second material;
a peripheral circuit area including a transistor having a single-layer gate electrode formed above said semiconductor substrate, said single-layer gate electrode being comprised of said first material;
a first border area including: a first isolation region formed in said semiconductor substrate for isolating said non-volatile memory area and said peripheral circuit area; a first residual pattern including an insulating film directly formed on said first isolation region in entire direct contact thereto, and made of a same layer as said inter-electrode insulating film and a single conductive layer formed on said insulating film in direct contact thereto, and a first redundant insulating side wall comprised of a same layer as said first insulating side walls and formed on a side wall of said first residual pattern on a side of said non-volatile memory area; and
wherein said floating gate is comprised of a first polysilicon and wherein said first residual pattern is free of said first polysilicon.
2. The non-volatile semiconductor memory device according to claim 1 , wherein:
said peripheral circuit area has a second insulating side wall comprising a third material formed on side walls of said single-layer gate electrode; and
said first border area has an insulating upper layer comprising said third material and formed on said first redundant insulating side wall.
3. The non-volatile semiconductor memory device according to claim 1 , further comprising:
a laminated gate transistor area including a laminated gate transistor having a laminated gate electrode including a floating gate, an inter-electrode insulating film and a control gate stacked above said semiconductor substrate, similar to said non-volatile memory area, and having first insulating side walls formed on side walls of said laminated gate electrode, said laminated gate transistor using said floating gate as a gate electrode; and
a second border area including: a second isolation region formed in said semiconductor substrate for isolating said laminated gate transistor area and said peripheral circuit area; a second conductive pattern including a portion made of a same layer as the layer of said control gate and formed above said semiconductor substrate including said second isolation region; and a second redundant insulating side wall made of a same layer as the layer of said first insulating side wall and formed on a side wall of said second conductive pattern on a side of said laminated gate transistor area.
4. The non-volatile semiconductor memory device according to claim 3 , wherein said second conductivity pattern includes a lower layer portion made of a same layer as a layer of said floating gate and an upper layer portion made of a same layer as the layer of said control gate, on a side of said laminated gate transistor area, and includes only a portion made of a same layer as the layer of said control gate on a side of said peripheral circuit area.
5. The non-volatile semiconductor memory device according to claim 1 , further comprising an insulating film fence preventive structure near at ends of an active region in said non-volatile memory area, said insulating film fence preventive structure including a dummy floating gate made of a same layer of a layer of said floating gate, an insulating film made of a same layer as a layer of said inter-electrode insulating film and formed on an upper surface and a side wall of said dummy floating gate not facing said active region, and a dummy control gate made of a same layer as the layer of said control gate.
6. A non-volatile semiconductor memory device comprising:
a semiconductor substrate;
a non-volatile memory area including a non-volatile memory cell having a gate electrode including a floating gate, an inter-electrode insulating film and a control gate stacked above said semiconductor substrate and having first insulating side walls made of a first insulating material, and formed on side walls of said gate electrode;
a peripheral circuit area including a transistor having a single-layer gate electrode formed above said semiconductor substrate and second insulating side walls made of a second insulating material different from the first insulating material, and formed on side walls of said single-layer gate electrode, said single-layer gate electrode being made of a same layer as a layer of said control gate; and
a first border area including: a first isolation region formed in said semiconductor substrate for isolating said non-volatile memory area and said peripheral circuit area; a first conductive pattern including a portion made of a same layer as the layer of said control gate and formed above said semiconductor substrate including said first isolation region; and a first redundant insulating side wall made of said first insulating material and formed on a side wall of said first conductive pattern on a side of said non-volatile memory area and a second redundant insulating layer made of said second insulating material and formed on said first redundant insulating side wall.
7. The non-volatile semiconductor memory device according to claim 6 , wherein: said first insulating material is silicon nitride, and said second insulating material is silicon oxide.
8. The non-volatile semiconductor memory device according to claim 6 , wherein said first conductive pattern includes lamination of layers made of same layers as said gate electrode of said non-volatile memory cell.
9. The non-volatile semiconductor memory device according to claim 6 , further comprising:
a laminated gate transistor area including a laminated gate transistor having a laminated gate electrode including a floating gate, an inter-electrode insulating film and a control gate stacked above said semiconductor substrate, similar to said non-volatile memory area, and having first insulating side walls formed on side walls of said laminated gate electrode, said laminated gate transistor using said floating gate as a gate electrode; and
a second border area including: a second isolation region formed in said semiconductor substrate for isolating said laminated gate transistor area and said peripheral circuit area; a second conductive pattern including a portion made of a same layer as the layer of said control gate and formed above said semiconductor substrate including said second isolation region; and a second redundant insulating side wall made of a same layer as the layer of said first insulating side wall and formed on a side wall of said second conductive pattern on a side of said laminated gate transistor area.
10. The non-volatile semiconductor memory device according to claim 9 , wherein said second conductivity pattern includes a lower layer portion made of a same layer as a layer of said floating gate and an upper layer portion made of a same layer as the layer of said control gate, on a side of said laminated gate transistor area, and includes only a portion made of a same layer as the layer of said control gate on a side of said peripheral circuit area.
11. The non-volatile semiconductor memory device according to claim 6 , further comprising an insulating film fence preventive structure near at ends of an active region in said non-volatile memory area, said insulating film fence preventive structure including a dummy floating gate made of a same layer of a layer of said floating gate, an insulating film made of a same layer as a layer of said inter-electrode insulating film and formed on an upper surface and a side wall of said dummy floating gate not facing said active region, and a dummy control gate made of a same layer as the layer of said control gate.
12. The non-volatile semiconductor memory device according to claim 1 , wherein said insulating film is entirely planar.