IP Library Granted Patent US 7,725,802
Granted Patent B2
US 7,725,802 · App. 11/201,796 · Granted May 25, 2010

Code design and implementation improvements for low density parity check codes for multiple-input multiple-output channels

Assignee: The DIRECTV Group, Inc.
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Quick Facts
Patent No.
US 7,725,802
App. No.
11/201,796
Granted
May 25, 2010
Kind
B2
Abstract

Methods and systems for designing LDPC codes are disclosed. A method in accordance with the present invention comprises configuring a plurality (M) of parallel accumulation engines, accumulating a first information bit at a first set of specific parity bit addresses using the accumulation engines, increasing a parity bit address for each of the parity bit addresses by a pre-determined offset for each new information bit, accumulating subsequent information bits at parity bit addresses offset from the parity bit addresses by a pre-determined offset until an M+1 information bit is reached, accumulating the next M information bits at a second set of specific parity bit addresses using the parallel accumulation engines, increasing a parity bit address for each member of the second set of parity bit addresses by the pre-determined offset for each new information bit; and repeating accumulating and increasing the addresses until the information bits are exhausted.

Claims (14)

1. A method for generating Low Density Parity Check (LDPC) codes from input data comprising a plurality of information bits into parity bits of the LDPC codes for use in broadcast systems, comprising:

a) accepting the plurality of information bits at a LDPC encoder;

b) accumulating a first information bit at a first set of specific parity bit addresses using the LDPC encoder;

c) increasing a parity bit address for each member of the first set of specific parity bit addresses by a pre-determined offset for each new information bit;

d) accumulating subsequent information bits at parity bit addresses that are offset from the specific parity bit addresses by a pre-determined offset until an M+1 information bit is reached;

e) accumulating the next M information bits at a second set of specific parity bit addresses using the LDPC encoder;

f) increasing a parity bit address for each member of the second set of specific panty bit addresses by the pre-determined offset for each new information bit; and

repeating (e) through (f) until the information bits are exhausted.

2. The method of claim 1 , wherein accepting the plurality of information bits at the LDPC encoder comprises accepting the plurality of information bits in a Multiple-Input, Multiple-Output (MIMO) system.

3. The method of claim 2 , wherein accumulating the subsequent information bits at parity bit addresses that are offset from the specific parity bit addresses by a different pre-determined offset, the different pre-determined offset being code-dependent.

4. The method of claim 3 , further comprising accumulating the parity bits by adding each parity bit address to the immediately preceding parity bit address.

5. The method of claim 4 , further comprising transmitting the LDPC codes by a plurality of antennas.

6. The method of claim 5 , further comprising limiting a number of bit nodes in the parity check matrix to 400.

7. The method of claim 5 , wherein the LDPC codes are short block length codes.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 12, 2009
From: THE DIRECTV GROUP, INC.
To: DTVG LICENSING, INC.
Reel/Frame 022668/0491 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 11, 2005
From: EROZ, MUSTAFA; LEE, LIN-NAN; SUN, FENG-WEN
To: DIRECTV GROUP, INC., THE
Reel/Frame 016892/0183 →
Continuity (2)
Provisional Application 6060153300 · Aug 13, 2004
Related Publication 20060036928A1 · Feb 16, 2006