IP Library Granted Patent US 7,547,971
Granted Patent B2
US 7,547,971 · App. 11/202,352 · Granted Jun 16, 2009

Semiconductor integrated circuit device

Assignees: Renesas Technology Corp.; Hitachi ULSI Systems Co., Ltd.
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Quick Facts
Patent No.
US 7,547,971
App. No.
11/202,352
Granted
Jun 16, 2009
Kind
B2
Abstract

Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting electrodes are provided on the organic insulating film. At least one conductive layer for electrically connecting the first and second external connecting electrodes and the first electrodes is placed on the organic insulating film.

Claims (19)

1. A semiconductor integrated circuit device, comprising:

a semiconductor substrate;

circuit elements and wirings which are provided on one main surface of the semiconductor substrate and constitute a circuit;

first electrodes provided on the one main surface and electrically connected to the circuit, wherein said first electrodes is disposed on a top layer of said circuit;

an organic insulating film provided on the circuit except for openings on the surfaces of the first electrodes;

a conductive layer disposed on the organic insulating film, said conductive layer is connected through said openings with said first electrode;

first and second external connecting electrodes provided on said conductive layer, wherein said conductive layer used to electrically connect the first and second external connecting electrodes to the first electrodes.

2. The semiconductor integrated circuit device according to claim 1 , wherein the first and second external connecting electrodes are larger than those of the first electrodes in area.

3. The semiconductor integrated circuit device according to claim 1 , wherein the first and second external connecting electrodes are bump electrodes, respectiyely.

4. The semiconductor integrated circuit device according to claim 1 , wherein the first electrodes are bonding pads formed on the top circuit layer, respectively.

5. The semiconductor integrated circuit device according to claim 1 , wherein the conductive layer is a rewiring layer.

6. The semiconductor integrated circuit device according to claim 1 , wherein the semiconductor substrate is quadrangular, and the conductive layer is formed so as to be substantially identical to the length of one side of the semiconductor substrate or longer than the length thereof.

7. The semiconductor integrated circuit device according to claim 1 , wherein the first and second external connecting electrodes are both supplied with the same voltage from an external circuit.

8. The semiconductor integrated circuit device according to claim 7 , wherein the first and second external connecting electrodes are respectively supplied with a source voltage from an external circuit.

9. The semiconductor integrated circuit device according to claim 7 , wherein the first and second external connecting electrodes are respectively supplied with a circuit ground voltage from an external circuit.

10. The semiconductor integrated circuit device according to claim 1 , further including second electrodes provided on the one main surface and electrically connected to the circuit and said second electrodes are disposed on a top layer of said circuit,

wherein the first and second external connecting electrodes are connected to the conductive layer and the first and second electrodes are connected to the conductive layer.

11. The semiconductor integrated circuit device according to claim 1 , wherein the first and second external connecting electrodes include solder balls.

12. The semiconductor integrated circuit device according to claim 1 , wherein the conductive layers are connected with the wirings provided on the one main surface of the semiconductor substrate through a via hole formed in the organic insulating film.

Assignments (5)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 9, 2014
From: HITACHI ULSI SYSTEMS CO., LTD.
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 032859/0252 →
MERGER Recorded Jul 7, 2010
From: RENESAS TECHNOLOGY CORP.
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 024662/0280 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 12, 2005
From: SHINOZAKI, MASAO; NISHIMOTO, KENJI; AKIOKA, TAKASHI; KOHARA, YUTAKA; ASARI, SANAE; MIYATA, SHUSAKU; NAKAZATO, SHINJI
To: HITACHI, LTD.; HITACHI ULSI SYSTEMS CO., LTD.
Reel/Frame 016887/0471 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 12, 2005
From: HITACHI, LTD.
To: RENESAS TECHNOLOGY CORP.
Reel/Frame 016887/0612 →
Priority Claims (2)
JP 2000-383728 · Dec 18, 2000 · national
JP 2001-161630 · May 30, 2001 · national
Continuity (2)
Continuation 1036266100
Related Publication 20060006480A1 · Jan 12, 2006