IP Library Granted Patent US 8,260,240
Granted Patent B2
US 8,260,240 · App. 11/204,631 · Granted Sep 4, 2012

Single path architecture and automatic gain control (SAGC) algorithm for low power SDARS receivers

Assignee: Agere Systems Inc.
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Quick Facts
Patent No.
US 8,260,240
App. No.
11/204,631
Filed
Aug 16, 2005
Granted
Sep 4, 2012
Kind
B2
Art Unit
2618
USPC
455/245.1
Abstract

An automatic gain control (AGC) for use in a digital radio receiver that allows at least two types of input signal to be processed using a single receiver front end by supporting two modes of operation, each optimized for one particular signal type, and a third mode not optimized for either. The AGC enables smooth switching between the optimized modes of operation via the non-optimized mode. By measuring a difference in the strength between the demodulated signals, and comparing that to two preset values, the AGC controls which mode of operation to place the receiver in. Modes of operation are maintained by adjusting the gain of a variable gain amplifier (VGA), so that an appropriate incoming signal is amplified to a level that is suitable for an analogue-to-digital (ADC) converter. The AGC is compatible with existing satellite digital audio radio system (SDARS) transmission capabilities.

Claims (36)

1. A method for operating an automatic gain control coupled to a variable gain amplifier, the automatic gain control being operable to control the variable gain amplifier in at least three modes of operation, the method comprising the steps of:

a) operating the automatic gain control in a third mode of operation adapted for both said first signal modulation type and said second signal modulation type;

b) comparing a first output level corresponding to said first signal modulation type to a second output level corresponding to said second signal modulation type; and

c) transitioning the automatic gain control from said third mode to one of a first mode of operation adapted for said first signal modulation type and a second mode of operation adapted for said second signal modulation type responsive to said comparing step;

wherein the variable gain amplifier is shared by both said first signal having the first signal modulation type and said second signal having the second signal modulation type in each of the at least three modes of operation comprising the first mode of operation adapted for said first signal modulation type, the second mode of operation adapted for said second signal modulation type, and the third mode of operation adapted for both said first signal modulation type and said second signal modulation type.

2. The method of claim 1 , further comprising the steps of:

d) transitioning the automatic gain control from said first mode of operation to said third mode of operation responsive to said comparing step; and

e) transitioning the automatic gain control from said second mode of operation to said third mode of operation responsive to said comparing step.

3. The method of claim 2 , wherein step b) comprises calculating a difference between said first output level and said second output level, and wherein step c) comprises transitioning to said first mode dependent on said difference being less than a first constant and transitioning to said second mode dependent on said difference exceeding a second constant.

4. The method of claim 3 , wherein step d) occurs dependent on said difference exceeding said first constant, and step e) occurs dependent on said difference being less than said second constant.

5. The method of claim 4 , wherein step c) comprises transitioning from said third mode to said first mode dependent on said difference being less than said first constant minus a preset hysteresis off-set value, and step d) comprises transitioning from said first mode to said third mode dependent on said difference exceeding said first constant plus said preset hysteresis off-set value.

6. The method of claim 2 , further comprising a fourth mode of operation adapted for said second signal modulation type, a first track signal corresponding to the presence of said first signal modulation type and a second track signal corresponding to the presence of said second signal modulation type and further comprising the steps of f) transitioning from said first mode to said fourth mode dependent on said first track signal being absent; and g) transitioning from said fourth mode to said third mode dependent on said second track signal being absent.

7. The method of claim 6 , further comprising the step of h) transitioning from said third mode to said fourth mode dependent on said first track signal being absent.

8. The method of claim 1 , wherein step c) further comprises delaying transitioning for a preset time after a transition condition is initially established.

9. The method of claim 1 , wherein the output level of a given signal modulation type comprises power of the given signal modulation type after demodulation.

10. The method of claim 1 , wherein said first signal modulation type comprises a time division multiplexed (TDM) signal and said second signal modulation type comprises a coded orthogonal frequency division multiplexed (COFDM) signal.

11. A device, comprising:

an automatic gain control coupled to a variable gain amplifier, the automatic gain control being operable to control the variable gain amplifier in at least three modes of operation; and

a processor programmed to be capable of:

operating said automatic gain control in a third mode of operation adapted for both the first signal modulation type and the second signal modulation type;

comparing a first output level corresponding to said first signal modulation type to a second output level corresponding to said second signal modulation type; and

transitioning said automatic gain control from said third mode to one of a first mode of operation adapted for said first signal modulation type and a second mode of operation adapted for use in connection with said second signal modulation type responsive to said comparing step;

wherein the variable gain amplifier is shared by both said first signal having said first signal modulation type and said second signal having said second signal modulation type in each of the at least three modes of operation comprising the first mode of operation adapted for said first signal modulation type, the second mode of operation adapted for said second signal modulation type, and the third mode of operation adapted for both said first signal modulation type and said second signal modulation type.

12. The device of claim 11 , wherein said processor is further capable of transitioning said automatic gain control from said first mode of operation to said third mode of operation responsive to said comparison; and transitioning said automatic gain control from said second mode of operation to said third mode of operation responsive to said comparison.

13. The device of claim 12 , wherein said processor is further capable of calculating a difference between said first output level and said second output level, and wherein said transitioning said automatic gain control from said third mode of operation to said first mode of operation occurs dependent on said difference being less than a first constant and said transitioning said automatic gain control from said third mode of operation to said second mode dependent on said difference exceeding a second constant.

14. The device of claim 13 , wherein said processor is further capable of transitioning said automatic gain control from said first mode of operation to said third mode of operation dependent on said difference exceeding said first constant, and transitioning said automatic gain control from said second mode of operation to said third mode of operation dependent on said difference being less than said second constant.

15. The device of claim 13 , wherein said processor is further capable of transitioning said automatic gain control from said third mode to said first mode dependent on said difference being less than said first constant minus a preset hysteresis off-set value, and transitioning said automatic gain control from said first mode to said third mode dependent on said difference exceeding said first constant plus said preset hysteresis off-set value.

16. The device of claim 12 , wherein said automatic gain control further comprises a fourth mode of operation adapted for said second signal modulation type, a first track signal corresponding to the presence of said first signal modulation type and a second track signal corresponding to the presence of said second signal modulation type and wherein said processor is further capable of transitioning said automatic gain control from said first mode of operation to said fourth mode of operation dependent on said first track signal being absent; and transitioning said automatic gain control from said fourth mode of operation to said third mode of operation dependent on said second track signal being absent.

17. The device of claim 16 , wherein said processor is further capable of transitioning said automatic gain control from said third mode of operation to said fourth mode of operation dependent on said first track signal being absent.

18. The device of claim 11 , wherein said processor is further capable of storing a preset time value, and wherein said transitioning is dependent on said comparison maintaining a transition condition for a time at least equal to said preset time value.

19. The device of claim 11 , wherein the output level of a given signal modulation type comprises power of the given signal type after demodulation.

20. The device of claim 11 , wherein said first signal modulation type comprises a time division multiplexed (TDM) signal and said second signal modulation type comprises a coded orthogonal frequency division multiplexed (COFDM) signal.

21. The device of claim 11 , wherein the variable gain amplifier is in a receiver front-end shared by both said first signal having said first signal modulation type and said second signal having said second signal modulation type in each of the at least three modes of operation, and wherein the shared receiver front-end further comprises an antenna coupled to the variable gain amplifier and shared by both said first signal having said first signal modulation type and said second signal having said second signal modulation type in each of the at least three modes of operation.

22. The device of claim 21 , wherein the shared receiver front-end further comprises a analogue-to-digital converter shared by both said first signal having said first signal modulation type and said second signal having said second signal modulation type in each of the at least three modes of operation.

23. The device of claim 21 , wherein the shared receiver front-end is coupled to at least first and second receiver back-ends respectively corresponding to the first signal modulation type and the second signal modulation type.

24. The device of claim 23 , wherein the first receiver back-end comprises one or more digital down converters corresponding to the first signal modulation type and one or more digital demodulators corresponding to the first signal modulation type, and wherein the second receiver-back end comprises one or more digital down converters corresponding to the second signal modulation type and one or more digital demodulators corresponding to the second signal modulation type.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 09/05/2018 PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0133. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0456 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0133 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035365/0634 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 16, 2005
From: MALKEMES, ROBERT; ORLANDO, DENIS; SONG, JIE; ZHONG, ERIC
To: AGERE SYSTEMS INC.
Reel/Frame 016896/0297 →
Continuity (1)
Related Publication 20070041481A1 · Feb 22, 2007