System and method for circuit noise analysis
Systems and methods for the noise analysis of circuits are presented. These systems and methods may allow a circuit or circuit design to be analyzed for possible noise failures in a block of logic caused by sources. outside the block. More particularly, these systems and methods may generate an abstract file for one or more blocks of a circuit. These abstract files may include noise tolerances for input pins and bi-directional pins of a block, along with noise tolerances for those output pins of the block which also feed to an input of one or more gates internal to the block. Using these noise abstracts a unit of the circuit may be analyzed, or the circuit itself may be analyzed for possible noise induced failures.
1. A method for performing noise analysis of a circuit, comprising:
forming a set of noise abstracts for a set of blocks of logic of a circuit, each of the set of noise abstracts corresponding to a block of logic in the set of blocks of logic, wherein each of the set of noise abstracts for the set of blocks of logic of the circuit is formed by performing a transistor level analysis of the block of logic corresponding to the noise abstract, each block of logic in the set of blocks of logic comprises a set of input pins, a set of output pins and a set of bi-directional pins and each of the set of noise abstracts for the set of blocks of logic comprises a noise tolerance for each of the set of input-pins of the corresponding block of logic, a noise tolerance for each of the set of bi-directional-pins of the corresponding block of logic and a noise tolerance level for each of the set of output pins of the corresponding block of logic which feeds an input of internal logic of the corresponding block of logic and the noise tolerance for each of the set of input-pins of the corresponding block of logic, the noise tolerance for each of the set of bi-directional-pins of the corresponding block of logic and the noise tolerance level for each of the set of output pins of the corresponding block of logic which feeds an input of internal logic of the corresponding block of logic is a single voltage independent of noise pulse width; and
performing a noise analysis of the circuit utilizing the set of noise abstracts.
2. The method of claim 1 , further comprising forming a set of noise abstracts for a set of units of the circuit, wherein each unit comprises one or more blocks in the set of blocks of logic.
3. The method of claim 2 , wherein forming the set of noise abstracts for the set of units of the circuit is done using resistor/capacitor (R/C) analysis.
4. The method of claim 1 , wherein performing a noise analysis of the circuit further comprises determining if a calculated noise level at a pin in the set of input pins of a block of logic, the set of output pins of the block of logic which feed an input of internal logic of the block of logic or the set of bi-directional pins exceeds the noise tolerance for the pin in the noise abstract associated with the block.
5. The method of claim 4 , wherein performing the noise analysis of the circuit is done using resistor/capacitor (R/C) analysis.
6. The method of claim 4 , wherein each of the set of noise abstracts for the set of blocks of logic comprises a capacitance for each of the set of input-pins of the corresponding block of logic, a capacitance and drive resistance for each of the set of bi-directional-pins of the corresponding block of logic and a drive resistance for each of the set of output pins.
7. The method of claim 6 , wherein performing a noise analysis of the circuit is done using a set of equivalent circuits, wherein each equivalent circuit represents a corresponding block of the set of blocks of logic with a set of resistors, capacitors or voltage sources.
8. A method for performing noise analysis of a circuit, comprising:
forming a set of noise abstracts for a set of blocks of logic of a circuit, each of the set of noise abstracts corresponding to a block of logic in the set of blocks of logic, wherein each of the set of noise abstracts for the set of blocks of logic of the circuit is formed by performing a transistor level analysis of the block of logic corresponding to the noise abstract, each block of logic in the set of blocks of logic comprises a set of input pins, a set of output pins and a set of bi-directional pins and each of the set of noise abstracts for the set of blocks of logic comprises a noise tolerance for each of the set of input-pins of the corresponding block of logic, a noise tolerance for each of the set of bi-directional-pins of the corresponding block of logic and a noise tolerance level for each of the set of output pins of the corresponding block of logic which feeds an input of internal logic of the corresponding block of logic and the noise tolerance for each of the set of input-pins of the corresponding block of logic, the noise tolerance for each of the set of bi-directional-pins of the corresponding block of logic and the noise tolerance level for each of the set of output pins of the corresponding block of logic feeds an input of internal logic of the corresponding block of logic is a noise rejection curve of noise amplitude versus noise pulse width; and
performing a noise analysis of the circuit utilizing the set of noise abstracts.
9. The method of claim 8 , further comprising forming a set of noise abstracts for a set of units of the circuit, wherein each unit comprises one or more blocks in the set of blocks of logic.
10. The method of claim 9 , wherein forming the set of noise abstracts for the set of units of the circuit is done using resistor/capacitor (R/C) analysis.
11. The method of claim 8 , wherein performing a noise analysis of the circuit further comprises determining if a calculated noise level at a pin in the set of input pins of a block of logic, the set of output pins of the block of logic which feed an input of internal logic of the block of logic or the set of bi-directional pins exceeds the noise tolerance for the pin in the noise abstract associated with the block.
12. The method of claim 11 , wherein performing the noise analysis of the circuit is done using resistor/capacitor (R/C) analysis.
13. The method of claim 11 , wherein each of the set of noise abstracts for the set of blocks of logic comprises a capacitance for each of the set of input-pins of the corresponding block of logic, a capacitance and drive resistance for each of the set of bi-directional-pins of the corresponding block of logic and a drive resistance for each of the set of output pins.
14. The method of claim 11 , wherein performing a noise analysis of the circuit is done using a set of equivalent circuits, wherein each equivalent circuit represents a corresponding block of the set of blocks of logic with a set of resistors, capacitors or voltage sources.
15. A computer readable medium, having instructions embodied thereon for performing noise analysis of a circuit, the instructions translatable for:
forming a set of noise abstracts for a set of blocks of logic of a circuit, each of the set of noise abstracts corresponding to a block of logic in the set of blocks of logic, wherein each of the set of noise abstracts for the set of blocks of logic of the circuit is formed by performing a transistor level analysis of the block of logic corresponding to the noise abstract, each block of logic in the set of blocks of logic comprises a set of input pins, a set of output pins and a set of bi-directional pins and each of the set of noise abstracts for the set of blocks of logic comprises a noise tolerance for each of the set of input-pins of the corresponding block of logic, a noise tolerance for each of the set of bi-directional-pins of the corresponding block of logic and a noise tolerance level for each of the set of output pins of the corresponding block of logic which feeds an input of internal logic of the corresponding block of logic and the noise tolerance for each of the set of input-pins of the corresponding block of logic, the noise tolerance for each of the set of bi-directional-pins of the corresponding block of logic and the noise tolerance level for each of the set of output pins of the corresponding block of logic which feeds an input of internal logic of the corresponding block of logic is a single voltage independent of noise pulse width; and
performing a noise analysis of the circuit utilizing the set of noise abstracts.
16. The computer readable medium of claim 15 , wherein the instructions are further translatable for forming a set of noise abstracts for a set of units of the circuit, wherein each unit comprises one or more blocks in the set of blocks of logic.
17. The computer readable medium of claim 15 , wherein forming the set of noise abstracts for the set of units of the circuit is done using resistor/capacitor (R/C) analysis.
18. The computer readable medium of claim 15 , wherein performing a noise analysis of the circuit further comprises determining if a calculated noise level at a pin in the set of input pins of a block of logic, the set of output pins of the block of logic which feed an input of internal logic of the block of logic or the set of bi-directional pins exceeds the noise tolerance for the pin in the noise abstract associated with the block.
19. The computer readable medium of claim 18 , wherein performing the noise analysis of the circuit is done using resistor/capacitor (R/C) analysis.
20. The computer readable medium of claim 18 , wherein each of the set of noise abstracts for the set of blocks of logic comprises a capacitance for each of the set of input-pins of the corresponding block of logic, a capacitance and drive resistance for each of the set of bi-directional-pins of the corresponding block of logic and a drive resistance for each of the set of output pins.
21. The computer readable medium of claim 20 , wherein performing a noise analysis of the circuit is done using a set of equivalent circuits, wherein each equivalent circuit represents a corresponding block of the set of blocks of logic with a set of resistors, capacitors or voltage sources.
22. A computer readable medium, having instructions embodied thereon for performing noise analysis of a circuit, the instructions translatable for:
forming a set of noise abstracts for a set of blocks of logic of a circuit, each of the set of noise abstracts corresponding to a block of logic in the set of blocks of logic, wherein each of the set of noise abstracts for the set of blocks of logic of the circuit is formed by performing a transistor level analysis of the block of logic corresponding to the noise abstract, each block of logic in the set of blocks of logic comprises a set of input pins, a set of output pins and a set of bi-directional pins and each of the set of noise abstracts for the set of blocks of logic comprises a noise tolerance for each of the set of input-pins of the corresponding block of logic, a noise tolerance for each of the set of bi-directional-pins of the corresponding block of logic and a noise tolerance level for each of the set of output pins of the corresponding block of logic which feeds an in input of internal logic of the corresponding block of logic and the noise tolerance for each of the set of input-pins of the corresponding block of logic, the noise tolerance for each of the set of bi-directional-pins of the corresponding block of logic and the noise tolerance level for each of the set of output pins of the corresponding block of logic feeds an input of internal logic of the corresponding block of logic is a noise rejection curve of noise amplitude versus noise pulse width; and
performing a noise analysis of the circuit utilizing the set of noise abstracts.
23. The computer readable medium of claim 22 , wherein the instructions are further translatable for forming a set of noise abstracts for a set of units of the circuit, wherein each unit comprises one or more blocks in the set of blocks of logic.
24. The computer readable medium of claim 23 , wherein forming the set of noise abstracts for the set of units of the circuit is done using resistor/capacitor (R/C) analysis.
25. The computer readable medium of claim 22 , wherein performing a noise analysis of the circuit further comprises determining if a calculated noise level at a pin in the set of input pins of a block of logic, the set of output pins of the block of logic which feed an input of internal logic of the block of logic or the set of bi-directional pins exceeds the noise tolerance for the pin in the noise abstract associated with the block.
26. The computer readable medium of claim 25 , wherein performing the noise analysis of the circuit is done using resistor/capacitor (R/C) analysis.
27. The computer readable medium of claim 25 , wherein each of the set of noise abstracts for the set of blocks of logic comprises a capacitance for each of the set of input-pins of the corresponding block of logic, a capacitance and drive resistance for each of the set of bi-directional-pins of the corresponding block of logic and a drive resistance for each of the set of output pins.
28. The computer readable medium of claim 27 , wherein performing a noise analysis of the circuit is done using a set of equivalent circuits, wherein each equivalent circuit represents a corresponding block of the set of blocks of logic with a set of resistors, capacitors or voltage sources.